Grenoble, France Wolfgang Rosenstiel, Kazutoshi Wakabayashi (Eds.):
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009.
ACM 2009, ISBN 978-1-60558-628-1
Framworks for platform modeling and exploration
Tools for embedded software design
System level modeling and simulation
- Weichen Liu, Zonghua Gu, Jiang Xu, Yu Wang, Mingxuan Yuan:
An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.
- Marius Gligor, Nicolas Fournel, Frédéric Pétrot:
Using binary translation in event driven simulation for fast and flexible MPSoC simulation.
- Christian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler:
Configuration and control of SystemC models using TLM middleware.
- Heekyung Kim, Dukyoung Yun, Soonhoi Ha:
Scalable and retargetable simulation techniquesfor multiprocessor systems.
Architecture and routing for NoC
Application specific alogorithms and architectures
Embedded software systems
Power-aware design methodology
Synthesis and analysis for variation and reliability
Embedded system optimization across memory hierarchy
Efficient techniques for architecture simulation
- Yi-Len Lo, Mao Lin Li, Ren-Song Tsay:
Cycle count accurate memory modeling in system level design.
- Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran:
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.
- Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
TotalProf: a fast and accurate retargetable source code profiler.
- Daniel Christopher Powell, Björn Franke:
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators.
System level reconfiguration and architecture optimization
- Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto:
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.
- Lars Bauer, Muhammad Shafique, Jörg Henkel:
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.
- Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik:
Supporting RTL flow compatibility in a microarchitecture-level design framework.
Exploring the hardware software boundaries for MPSoC design
Perfomance analysis and optimization for heterogeneous multiprocesses system
- Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann:
Fast model-based test case classification for performance analysis of multimedia MPSoC platforms.
- Alexander Viehl, Michael Pressler, Oliver Bringmann:
Bottom-up performance analysis considering time slice based software scheduling at system level.
- Simon Schliecker, Rolf Ernst:
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems.
- Antonino Tumeo, Marco Branca, Lorenzo Camerini, Christian Pilato, Pier Luca Lanzi, Fabrizio Ferrandi, Donatella Sciuto:
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach.
Architecture and optimization of NoC
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