17. DAC 1980: Minneapolis, Minnesota, USA

• Edwin B. Hassler Jr.:
  Chairman's introduction. 1
  
• Jerrier A. Haddad:
  Keynote speaker. 2
  
• Lawrence M. Rosenberg:
  The evolution of design automation to meet the challanges of VLSI. 3-11
  
• David W. Hightower, Robert L. Boyd:
  A generalized channel router. 12-21
  
• Koji Sato, Hiroyoshi Shimoyama, Takao Nagai, Masaru Ozaki, Toshihiko Yahara:
  A "grid-free" channel router. 22-31
  
• David N. Deutsch, Paul Glick:
  An over-the-cell router. 32-39
  
• E. F. Chelotti, D. P. Bossie:
  Design automation at a large architect-engineer. 40-49
  
• Charles M. Eastman:
  System facilities for CAD databases. 50-56
  
• Thomas Sidle:
  Weaknesses of commercial data base management systems in engineering applications. 57-61
  
• Yacoub M. El-Ziq:
  A new test pattern generation system. 62-68
  
• Miron Abramovici, Melvin A. Breuer:
  Fault diagnosis based on effect-cause analysis: An introduction. 69-76
  
• Prabhakar Goel:
  Test generation costs analysis and projections. 77-84
  
• Jin H. Kim, Daniel P. Siewiorek:
  Issues in IC implementation of high level, abstract designs. 85-91
  
• Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki:
  A layout system for the random logic portion of MOS LSI. 92-99
  
• Frank R. Ramsay:
  Automation of design for uncommitted logic array. 100-107
  
• John M. Gould, Teddy M. Edge:
  The standard transistor array (STAR): Part I A two-layer metal semicustom design system. 108-113
  
• Jacob M. Miller:
  Inter-active graphic methods for automating mechanical engineering design and analyses. 114-128
  
• Arvind M. Patel:
  Computer-aided assignment of manufacturing tolerances. 129-133
  
• David W. Currier:
  Automation of sheet metal design and manufacturing. 134-138
  
• Thomas M. McWilliams:
  Verification of timing constraints on large digital systems. 139-147
  
• Arthur H. Altman, Alice C. Parker:
  The SLIDE simulator: A facility for the design and analysis of computer interconnections. 148-155
  
• Wendell E. Cory, William M. van Cleemput:
  Developments in verification of design correctness (A Tutorial). 156-164
  
• Robert Simpson Frew:
  A survey of space allocation algorithms in use in architectural design in the past twenty years. 165-174
  
• John Grason, Andrew W. Nagle:
  Digital test generation and design for testability. 175-189
  
• Lawrence H. Goldstein, Evelyn L. Thigpen:
  SCOAP: Sandia controllability/observability analysis program. 190-196
  
• J. Duane Northcutt:
  The design and implementation of fault insertion capabilities for ISPS. 197-209
  
• Manuel A. d'Abreu, Edward W. Thompson:
  An accurate functional level concurrent fault simulator. 210-217
  
• B. T. David:
  An integrated CAD system for architecture. 218-225
  
• Keiichi Sato, Charles L. Owen:
  A prestructuring model for system arrangement problems. 226-236
  
• V. Jayakumar:
  A data structure for interactive placement of rectangular objects. 237-242
  
• Walter Heyns, Willy Sansen, Herman Beke:
  A line-expansion algorithm for the general routing problem with a guaranteed solution. 243-249
  
• Fumiya Tada, Kiyoshi Yoshimura, Takashi Kagata, Takeyoshi Shirakawa:
  A fast maze router with iterative use of variable search space restriction. 250-254
  
• Michael J. Lorenzetti, Robert J. Smith II:
  An implementation of a saturated zone multi-layer printed circuit board router. 255-262
  
• Edward J. McGrath, Telle Whitney:
  Design integrity and immunity checking: A new look at layout verification and design rule checking. 263-268
  
• Shiu-Ping Chao, Yen-Son Huang, Lap Man Yam:
  A hierarchical approach for layout versus circuit consistency check. 269
  
• Shiu-Ping Chao, Yen-Son Huang, Lap Man Yam:
  A hierarchical approach for layout versus circuit consistency check. 270-276
  
• Takashi Mitsuhashi, Toshiaki Chiba, Makoto Takashima, Kenji Yoshida:
  An integrated mask artwork analysis system. 277-284
  
• Neil Weste, Bryan D. Ackland:
  An IC design station needs a high performance color graphic display. 285-291
  
• Dave Clary, Robert Kirk, Steve Sapiro:
  SIDS (A Symbolic Interactive Design System). 292-295
  
• Frank D. Skinner:
  Interactive wiring system. 296-308
  
• Günter Biehl, Werner Grass, P. S. Hall:
  Optimization of the influence of problem modifications on given microprogrammed controllers. 309-317
  
• Keith A. Duke, Klim Maling:
  Alex: A conversational, hierarchical logic design system. 318-327
  
• George M. Koppelman, Klim Maling:
  Verifying deep logic hierarchies with ALEX. 328-335
  
• Carl R. McCaw:
  Design automation and VLSI in the 80's (Panel Discussion). 336-337
  
• Jonathan Allen:
  A contemporary perspective on design automation and VLSI in the 80's (Position Statement). 338-339
  
• Charles W. Gwyn:
  Design automation trends for VLSI in the 1980s (Position Statement). 340
  
• R. M. Jacobs:
  Design automation and VLSI in the 80's (Position Statement). 341
  
• Benjamin Lee:
  Design tools for VLSI (Position Statement). 342
  
• A. Richard Newton:
  The VLSI design challenge of the 80's (Position Statement). 343-344
  
• Martin B. Roberts:
  VLSI - a challenge for system designers (Position Statement). 345
  
• Steve Sapiro:
  Desisn automation and VLSI in the 80's (Position Statement). 346-347
  
• Felix P. Mallmann:
  The management of engineering changes using the PRIMUS system. 348-361
  
• H. D. Schnurmann, R. M. Peters:
  An interactive test data system for LSI production testing. 362-366
  
• Gregory L. Smith, Sharon A. Stephens, Leonard L. Tripp, Wayne L. Warren:
  A tool to support design automation in batch manufacturing. 367-373
  
• Ernst Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven:
  High-speed concurrent fault simulation with vectors and scalars. 374-380
  
• Samiha Mourad:
  An optimized ATPG. 381-385
  
• Norbert Giambiasi, A. Miara, D. Muriach:
  Methods for generalized deductive fault simulation. 386-392
  
• Edward W. Thompson, Patrick G. Karger, W. R. Read Jr., Don Ross, John Smith, Richard von Blucher:
  The incorporation of functional level element routines into an existing digital simulation system. 394-401
  
• Sartaj Sahni, Atul Bhatt:
  The complexity of design automation problems. 402-411
  
• Wilm E. Donath:
  Complexity theory and design automation. 412-419
  
• Kenneth D. Yates:
  Design process analysis: A measurement and analysis technique. 420-421
  
• D. E. Bering:
  The electronics engineer's design station. 422-429
  
• P. Carmody, A. M. Barone, J. K. Morrell, A. Weiner, John L. Hennessy:
  An Interactive Graphics System for custom design. 430-439
  
• John B. Macdonald, Mary K. Podlecki, Milt J. Pappas:
  Technical documentation by "MAGIC" (Machine Aided Graphics for Illustration and Composition. 440-445
  
• Joe Dyer, Arijit Laha, Ernest J. Moran, William D. Smart:
  The use of graphics processors for circuit design simulation at GTE AE Labs. 446-450
  
• Glenn W. Cox, B. D. Carroll:
  The Standard Transistor Array (star) (Part II automatic cell placement techniques). 451-457
  
• Hiroshi Shiraishi, Fumiyasu Hirose:
  Efficient placement and routing techniques for master slice LSI. 458-464
  
• Valerie K. Smith, Robert J. Smith II, Phil A. Preston:
  Comet - a fast component placer. 465-471
  
• Frank Luebbert, Mike Ulrey:
  Gate assignment and pack placement: Two approaches compared. 472-482
  
• Sany M. Leinwand, T. Lamdan:
  Algebraic analysis of nondeterministic behavior. 483-493
  
• Mark G. Karpovsky, Stephen Y. H. Su:
  Detecting bridging and stuck-at faults at input and output pins of standard digital components. 494-505
  
• Albert E. Casavant, Daniel D. Gajski, David J. Kuck:
  Automatic design with dependence graphs. 506-515
  
• Paul Losleben:
  The real world of design automation - part III or The user's viewpoint chairman's introduction (Panel Discussion). 516
  
• R. A. Armstrong:
  A CAD user's perspective what gets done right wrong and not at all (Position Paper). 517
  
• A. E. Fitch:
  Will your bridge stand the load? (Position Paper). 518
  
• D. J. Garvin:
  Observations of a CAD user (Position Paper). 519
  
• Ikuo Nishioka, Takuji Kurimoto, Hisao Nishida, Seiji Yamamoto, Toru Chiba, Toshiaki Nagakawa, Takatsugu Fujioka, Masashi Uchino:
  An automatic routing system for high density multilayer printed wiring boards. 520-527
  
• L. C. Cote, Arvind M. Patel:
  The interchange algorithms for circuit placement problems. 528-534
  
• Antoni A. Szepieniec, Ralph H. J. M. Otten:
  The genealogical approach to the layout problem. 535-542
  
• John A. Darringer, William H. Joyner Jr.:
  A new look at logic synthesis. 543-549
  
• Sajjan G. Shiva:
  Combinational logic synthesis from an HDL description. 550-555
  
• J. Philip Singleton, Nigel R. Crocker:
  Practical automated design of LSI for large computers. 556-559
  
• Ernst Ulrich:
  Table lookup techniques for fast and flexible digital logic simulation. 560-563
  
• R. E. Powell:
  Justification and financial analysis for CAD. 564-571
  
• Paul R. Hanau, David R. Lenorovitz:
  A prototyping and simulation approach to interactive computer system design. 572-578
  
• Frank Bliss, George M. Hyman:
  Selecting and successfully implementing a turnkey computer graphics system. 579-584
  
• James A. Wilmore:
  A hierarchical bit-map format for the representation of IC mask data. 585-589
  
• Jirí Soukup, J. Royle:
  Cell map representation for hierarchical layout. 591-594
  
• Alfred E. Dunlop:
  SLIM-the translation of symbolic layouts into mask data. 595-602
  
• Ulrich Lauther:
  A data structure for gridless routing. 603-609
  
• Hao N. Nham, Ajoy K. Bose:
  A multiple delay simulator for MOS LSI circuits. 610-617
  
• Vishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes:
  A mixed-mode simulator. 618-625
  
• Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu:
  MIXS: A mixed level simulator for large digital system logic verification. 626-633
  
• Dan C. Nash, Keith Russell, Paul Silverman, Mary Thiel:
  Functional level simulation at Raytheon. 634-641
  
• Sam Bala Daram:
  Position statement - CAD for VLSI. 642
  

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