19. DAC 1982: Las Vegas, Nevada, USA

• Melvin A. Breuer:
  A survey of the state-of-the-art of design automation an invited presentation. 1
  
• Harold R. Marcotte:
  Robotics: The new automation tool. 2-8
  
• Thomas W. Williams:
  Design for testability. 9
  
• Lawrence A. O'Neill:
  A retrospective on software engineering in design automation. 10-14
  
• Robert Alan Friendenson, J. R. Breiland, T. J. Thompson:
  Designer's Workbench: Delivery of cad tools. 15-22
  
• T. J. Thompson:
  A utilitarian approach to CAD. 23-29
  
• Maciej J. Ciesielski, Edwin Kinnen:
  An analytical method for compacting routing area in integrated circuits. 30-37
  
• Raghunath Raghavan, Sartaj Sahni:
  Optimal single row router. 38-45
  
• Chi-Ping Hsu:
  A new two-dimensional routing algorithm. 46-50
  
• Gregory F. Pfister:
  The Yorktown Simulation Engine: Introduction. 51-54
  
• Monty Denneau:
  The Yorktown Simulation Engine. 55-59
  
• E. Kronstadt, Gregory F. Pfister:
  Software support for the Yorktown Simulation Engine. 60-64
  
• Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon:
  A logic simulation machine. 65-73
  
• Hriday R. Prasad:
  Workshop - industrial robotics. 74
  
• Clive A. Collins:
  IBM 3081 system overview and technology. 75-82
  
• Michael Monachino:
  Design verification system for large-scale LSI designs. 83-90
  
• Robert F. Woodward:
  Operational aspects of design automation for the IBM 3081. 91-95
  
• Vincent J. Freund Jr., J. A. Guerin:
  Automated conversion of design data for building the IBM 3081. 96-103
  
• Kenneth J. Supowit:
  A minimum-impact routing algorithm. 104-112
  
• Walter Heyns:
  The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers. 113-120
  
• Masayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara:
  A consideration of the number of horizontal grids used in the routing of a masterslice layout. 121-128
  
• Margaret Lie, Chi-Song Horng:
  A bus router for IC layout. 129-132
  
• Werner Grass:
  A depth-first branch-and-bound algorithm for optimal PLA folding. 133-140
  
• J. R. Egan, C. L. Liu:
  Optimal bipartite folding of PLA. 141-146
  
• Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  Techniques for programmable logic array folding. 147-155
  
• Bill Teel, Doran Wilde:
  A logic minimizer for VLSI PLA design. 156-162
  
• Richard L. Donze, Jacob Sanders, Michael Jenkins, George Sporzynski:
  Philo-a VLSI design system. 163-169
  
• Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law:
  Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design. 170-174
  
• Charles M. Fiduccia, Robert M. Mattheyses:
  A linear-time heuristic for improving network partitions. 175-181
  
• Thomas S. Payne, William M. van Cleemput:
  Automated partitioning of hierarchically specified digital systems. 182-192
  
• Leon I. Maissel, Daniel L. Ostapko:
  Interactive design language: A unified approach to hardware simulation, synthesis and documentation. 193-201
  
• Robert Piloty, Dominique Borrione:
  The conlan project: Status and future plans. 202-212
  
• James B. Rawlings:
  VHSIC HDL. 213
  
• Jere L. Sanborn:
  Evolution of the engineering design system data base. 214-218
  
• Erik Damm, H. Gethöffer, K. Kaiser:
  Hardware support for automatic routing. 219-223
  
• Ravi Nair, Se June Hong, Sandy Liles, Ray Villani:
  Global wiring on a wire routing machine. 224-231
  
• Larry Seiler:
  A hardware assisted design rule check architecture. 232-238
  
• Farhad Arbab, Larry Lichten, Michel A. Melkanoff:
  Toward CAM-oriented CAD. 239-245
  
• Kazuyuki Inoue, Masahiko Adachi, Toru Funayama:
  A layout system for high precision design of progressive die. 246-252
  
• William R. Heller, Gregory B. Sorkin, Klim Maling:
  The planar package planner for system designers. 253-260
  
• Ralph H. J. M. Otten:
  Automatic floorplan design. 261-267
  
• Jack Bennett:
  A database management system for design engineers. 268-273
  
• Randy H. Katz:
  A database approach for managing VLSI design data. 274-282
  
• David C. Smith, Barry S. Wagner:
  A low cost, transportable, data management system for LSI/VLSI design. 283-290
  
• Robert P. Larsen, James Allen Luisi, A. K. Singh:
  Aw expanded logic equation list for checkout. 291-299
  
• Samuel Chuquillanqui, Tomás Pérez Segovia:
  PAOLA: A tool for topological optimization of large PLAS. 300-306
  
• Joseph F. P. Luhukay, William J. Kubitz:
  A layout synthesis system for NMOS gate-cells. 307-314
  
• P. J. DesMarais, E. S. Y. Shew, Philip S. Wilcox:
  A functional level modelling language for digital simulation. 315-320
  
• Sajjan G. Shiva, J. A. Covington:
  Modular description/simulation/synthesis using DDL. 321-329
  
• James H. Tracey, Kovvali Surya Kumar:
  A hardware description language for processor based digital systems. 330-337
  
• T. H. Bruggere:
  Special purpose vs. general purpose hardware for da. 338
  
• H. G. Adshead:
  Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help? 339-344
  
• Markku Tamminen, Reijo Sulonen:
  The excell method for efficient geometric access to data. 345-351
  
• Gershon Kedem:
  The quad-CIF tree: A data structure for hierarchical on-line algorithms. 352-357
  
• David Grabel:
  Object data structures towards distributed graphics processing. 358-364
  
• Antoni A. Szepieniec:
  SAGA: An Experimental Silicon Assembler. 365-370
  
• Stephen Trimberger, James A. Rowson:
  Riot - a simple graphical chip assembly tool. 371-376
  
• John P. Gray, Irene Buchanan, Peter S. Robertson:
  Designing gate arrays using a silicon compiler. 377-383
  
• Yinghua Min, Stephen Y. H. Su:
  Testing functional faults in VLSI. 384-392
  
• John P. Hayes:
  A fault simulation methodology for VLSI. 393-399
  
• Ajoy K. Bose, Patrick Kozak, Chi-Yuan Lo, Hao N. Nham, Ernesto Pacas-Skewes, Kwok W. Wu:
  A fault simulator for MOS LSI circuits. 400-409
  
• Richard J. Lipton, J. D. Nash:
  Design automation algorithms: Research and applications. 410
  
• Tetsuo Asano:
  Parametric pattern router. 411-417
  
• Ronald L. Rivest, Charles M. Fiduccia:
  A "greedy" channel router. 418-424
  
• Robert K. Korn:
  An efficient variable-cost maze router. 425-431
  
• William A. Dees Jr., Patrick G. Karger:
  Automated rip-up and reroute techniques. 432-439
  
• Fontaine Richardson:
  Important criteria in selecting engineering work stations. 440-444
  
• Abe R. Shliferstein:
  Experiments using interactive color raster graphics for CAD. 445-452
  
• Lynne A. Price:
  Design of command menus for CAD systems. 453-459
  
• Kenneth H. Keller, A. Richard Newton, S. Ellis:
  A symbolic design system for integrated circuits. 460-466
  
• Richard J. Lipton, Stephen C. North, Robert Sedgewick, Jacobo Valdes, Gopalakrishnan Vijayan:
  ALI: A procedural language to describe VLSI layouts. 467-474
  
• Ronald L. Rivest:
  The "PI" (placement and interconnect) system. 475-481
  
• Prabhakar Goel, M. T. McMahon:
  Electronic Chip-in-Place Test. 482-488
  
• Kewal K. Saluja:
  An enhancement of lssd to reduce test pattern generation effort and increase fault coverage. 489-494
  
• Edward J. McCluskey:
  Verification testing. 495-500
  
• Yehuda E. Kalay:
  Modeling polyhedral solids bounded by multi-curved parametric surfaces. 501-507
  
• Gregory John Glass:
  A user interface for architectural design, a case study. 508-513
  
• Clive K. Liu, Charles M. Eastman:
  Design of a graphic processor for computer-aided drafting. 514-520
  
• G. Cosmai, Umberto Cugini, Piero Mussio, Amri Napolitano:
  An interactive drafting system based on two dimensional primitives. 521-529
  
• Michael H. Arnold, John K. Ousterhout:
  Lyra: A new approach to geometric layout rule checking. 530-536
  
• Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins:
  Cellular image processing techniques for VLSI circuit layout validation and routing. 537-543
  
• Makoto Takashima, Takashi Mitsuhashi, Toshiaki Chiba, Kenji Yoshida:
  Programs for verifying circuit connectivity of mos/lsi mask artwork. 544-550
  
• David Kaplan:
  A "non-restrictive" artwork verification program for printed circuit boards. 551-558
  
• R. W. Allen, M. M. Ervin-Willis, Rodham E. Tulloss:
  DORA: : CAD interface to automatic diagnostics. 559-565
  
• Catherine Bellon, A. Liothin, S. Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman:
  Automatic generation of microprocessor test programs. 566-573
  
• Pradip Bose, Jacob A. Abraham:
  Test generation for programmable logic arrays. 574-580
  
• Deepak K. Goel, Robert M. McDermott:
  An interactive testability analysis program - ITTAP. 581-586
  
• Ernst Ulrich, Dennis Hebert:
  Speed and accuracy in digital network simulation based on structural modeling. 587-593
  
• Robert B. Hitchcock Sr.:
  Timing Verification and the Timing Analysis program. 594-604
  
• Lionel Bening, Thomas A. Lane, Curtis R. Alexander, James E. Smith:
  Developments in logic network path delay analysis. 605-615
  
• Rathin Putatunda:
  Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips. 616-621
  
• Minoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada:
  Timing verification system based on delay time hierarchical nature. 622-628
  
• Vishwani D. Agrawal:
  Synchronous path analysis in MOS circuit simulator. 629-635
  
• Joseph Peled:
  Simplified data structure for "mini-based" turnkey CAD systems. 636-642
  
• Jeffrey Z. Gingerich, Michael P. Carroll, E. J. Chelius, Po-Kuan Lu:
  A hybrid CAD/CAM system for mechanical applications. 643-649
  
• Donald Robbins:
  Making the wire frame solid. 650-654
  
• Takashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka:
  A placement algorithm for polycell LSI and ITS evaluation. 655-662
  
• Klim Maling, Steven H. Mueller, William R. Heller:
  On finding most optimal rectangular package plans. 663-670
  
• G. J. Wipfler, Manfred Wiesel, Dieter A. Mlynski:
  A combined force and cut algorithm for hierarchical VLSI layout. 671-677
  
• Robert M. McDermott:
  Transmission gate modeling in an existing three-value simulator. 678-681
  
• Ekachai Lelarasmee, Alberto L. Sangiovanni-Vincentelli:
  Relax: A new circuit for large scale MOS integrated circuits. 682-687
  
• Michael R. Lightner, Gary D. Hachtel:
  Implication algorithms for MOS switch level functional macromodeling implication and testing. 691-698
  
• William A. Noon, Ken N. Robbins, M. Ted Roberts:
  A design system approach to data integrity. 699-705
  
• Xian-Long Hong, Ren-kung Yin, Xi-ling Liu:
  QCADS-a LSI CAD system for minicomputer. 706-711
  
• R. Alan Eustace, Amar Mukhopadhyay:
  A Deterministic finite automaton approach to design rule checking for VLSI. 712-717
  
• Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu:
  Arbitrarily-sized module location technique in the lop system. 718-726
  
• Hiroshi Shiraishi, Mitsuo Ishii, Shoichi Kurita, Masaaki Nagamine:
  ICAD/PCB: Integrated computer aided design system for printed circuit boards. 727-732
  
• Manfred Wiesel, Dieter A. Mlynski:
  Two-dimensional channel routing and channel intersection problems. 733-739
  
• John A. Nestor, Donald E. Thomas:
  Defining and implementing a multilevel design representation with simulation applications. 740-746
  
• Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima:
  An Interactive Simulation System for structured logic design - ISS. 747-754
  
• Kazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka:
  Logic simulation for LSI. 755-761
  
• J. D. Nash:
  VLSI design methodology workshop. 762
  
• Adam Pawlak:
  Digital logic modeling system based on MODLAN. 763-770
  
• Stacey J. Gelman:
  VEEP A VEctor Editor and Preparer. 771-776
  
• James E. Hassett:
  Automated layout in ASHLAR: An approach to the problems of "General Cell" layout for VLSI. 777-784
  
• Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo:
  Hierarchical top-down layout design method for VLSI chip. 785-791
  
• Lee F. Todd, J. M. Hansen, S. V. Pantulu, John L. Barron, D. J. Gilbert, R. J. Anderson, A. K. Biyani:
  CGALA-a multi technology Gate Array Layout system. 792-801
  
• T. Matsuda, Tomyyuki Fujita, K. Takamizawa, H. Mizumura, H. Nakamura, F. Kitajima, Satoshi Goto:
  LAMBDA: A quick, low cost layout design system for master-slice LSI s. 802-808
  
• Vijay Pitchumani, Edward P. Stabler:
  A formal method for computer design verification. 809-814
  
• Robert A. Mueller, Joseph Varghese:
  Formal semantics for the automated derivation of micro-code. 815-824
  
• Sany M. Leinwand:
  Logical correctness by construction. 825-831
  
• Fumihiro Maruyama, Takao Uehara, Nobuaki Kawato, Takao Saito:
  A verification technique for hardware designs. 832-841
  
• Yaohan Chu:
  Computer system design description. 842-850
  
• Philippe Basset, Gabriele Saucier:
  Top down design and testability of VLSI circuits. 851-857
  
• Nobuaki Kawato, Takao Uehara, Sadaki Hirose, Takao Saito:
  An interactive logic synthesis system based upon AI techniques. 858-864
  
• Ted M. Sparr:
  A language for a scientific and engineering database system. 865-871
  
• A. M. Beyls, B. Hennion, Jacques Lecourvoisier, Guy Mazaré, Alain Puissochet:
  A design methodology based upon symbolic layout and integrated cad tools. 872-878
  
• Mandalagiri S. Chandrasekhar, Melvin A. Breuer:
  Optimum placement of two rectangular blocks. 879-886
  
• Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer:
  On routing for custom integrated circuits. 887-893
  
• Ron Y. Pinter:
  On routing two-point nets across a channel. 894-902
  
• John K. Ousterhout, David M. Ungar:
  Measurements of a VLSI design. 903-908
  
• Saul Yermie Levy:
  Distributed computation for design aids. 909-915
  

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