21. DAC 1984: Albuquerque, New Mexico, USA
Patricia H. Lambert, Hillel Ofek, Lawrence A. O'Neill, Pat O. Pistilli, Paul Losleben, J. D. Nash, Dennis W. Shaklee, Bryan T. Preas, Harvey N. Lerman (Eds.): Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984. ACM/IEEE 1984 ISBN 0-8186-0542-1- Chin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam: The second generation motis mixed-mode simulator. 10-17
- Mahesh H. Doshi, Roderick B. Sullivan, Donald M. Schuler: THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator. 24-31
- Guy Dupenloup: A wire routing scheme for double-layer cell arrays. 32-37
- Takeshi Yoshimura: An efficient channel router. 38-44
- Gary W. Clow: A global routing algorithm for general cells. 45-51
- Charles H. Ng: A symbolic-interconnect router for custom IC design. 52-58
- W. H. Evans, Jean-Claude Ballegeer, Nguyen H. Duyet: ADL: An algorithmic design language for integrated circuit synthesis. 66-72
- Eric Slutz, Glen Okita, Jeanne Wiseman: Block description language (BDL): A structural description language. 81-85
- Daniel D. Gajski: Silicon compilers and expert systems for VLSI. 86-87
- Frederick Hinchliffe II, R. V. Alessi, J. Bunik, P. Catapano, M. Kubota, R. H. Dean, E. Dorsey, M. Leddell: Workshop introduction to gate array placement and routing packages. 89
- George D. M. Ross: Efficient implementation of experimental design systems. 109
- Martin Hardwick: Extending the relational database data model for design applications. 110-116
- Lee A. Hollaar, Brent E. Nelson, Tony M. Carter, Raymond A. Lorie: The structure and operation of a relational database system in a cell-oriented integrated circuit design system. 117-125
- Christopher Kingsley: A hiererachical, error-tolerant compactor. 126-132
- Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel: Chip layout optimization using critical path weighting. 133-136
- Hajimu Mori: Interactive compaction router for VLSI layout. 137-143
- John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor: Magic: A VLSI layout system. 152-159
- Walter S. Scott, John K. Ousterhout: Plowing: Interactive stretching and compaction in magic. 166-172
- Subrata Dasgupta, M. C. Graf, Robert A. Rasmussen, Ron G. Walther, Tom W. Williams: Chip partitioning aid: A design technique for partitionability and testability in VLSI. 203-208
- Erwin Trischler: An integrated design for testability and automatic test pattern generation system: An overview. 209-215
- Ralph K. Cavin III: Introduction to the SRC design sciences program. 216-217
- R. Smith: Basic turorial layout tools - what really is there. 219
- Masahiko Kawamura, Haruo Takagi, Kanji Hirabayashi: Functional verification of memory circuits from mask artwork data. 228-234
- P. T. Chapman, K. Clark Jr.: The scan line approach to design rules checking: Computational experiences. 235-241
- George J. Milne: A model for hardware description and verification. 251-257
- R. Alali, C. Durante, J. J. Mercier: A model for non interpreted structures of logical systems. 258-264
- Karl J. Lieberherr: Towards a standard hardware description language. 265-272
- Curtis H. Parks: IGES as an interchange format for integrated circuit design. 273-274
- Barry Jackson: A designing system for multi-family housing. 275-281
- Lloyd Wilkins: Module design verification system. 282-287
- Lynne A. Price: Studying the mouse for CAD systems. 288-293
- William H. Kao, Mohammad H. Movahed-Ezazi, Mark L. Sabiers: ARIES: A workstation based, schematic driven system for circuit design. 301-307
- Jean-Pierre Dussault, Chi-Chang Liaw, Michael M. Tong: A high level synthesis tool for MOS chip design. 308-314
- T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, Koichiro Ishihara: Polaris: Polarity propagation algorithm for combinational logic synthesis. 322-328
- Alice C. Parker, Fadi J. Kurdahi, Mitch J. Mlinar: A general methodology for synthesis and verification of register-transfer designs. 329-335
- Manuel A. d'Abreu, K. L. Cheong, C. T. Flanagan: Oracle - a simulator for Bipolar and MOS IC design. 343-349
- Jeffrey T. Deutsch, A. Richard Newton: A multiprocessor implementation of relaxation-based electrical circuit simulation. 350-357
- Daniel Etiemble, V. Adeline, Nguyen H. Duyet, J. C. Ballegeer: Micro-computer oriented algorithms for delay evaluation of MOS gates. 358-364
- John C. Foster: A unified CAD system for electronic design. 365-369
- Charles W. Rosenthal: Physical design and manufacturing information aspects aspects of the AT & T bell laboratories CAD system. 374-383
- A. Zingale, F. Kohn, F. Lynch, D. Kalbarsh: Workshop the semi-custom revolution: How to thrive or survive. 385
- Frederick Hinchliffe II: Commercial gate array physical design automation packages. 386-387
- Bill D. Richard: A standard cell initial placement strategy. 392-398
- Michael Palczewski: Performance of algorithms for initial placement. 399-404
- John Alan Roach: The rectangle placement language. 405-411
- Louis I. Steinberg, Tom M. Mitchell: A knowledge based approach to VLSI CAD the redesign system. 412-418
- Van E. Kelly: The CRITTER system: Automated critiquing of digital circuit designs. 419-425
- Theodore Sabety, David Elliot Shaw, Brian Mathies: The semi-automatic generation of processing element control paths for highly parallel machines. 441-446
- Vincent J. Freund Jr.: Managing a large volume of design/manufacturing/test data in a chip and module factory. 447-451
- W. J. Guillaume, A. Kurylo: MINUPROX - an advanced proximity correction technique for the IBM EL-2 electron beam tool. 452-453
- H. D. Schnurmann, L. J. Vidunas, R. M. Peters: An automated system for testing LSI memory chips. 454-458
- Stephen Nachtsheim: The Intel design automation system. 459-465
- Kit Tham, Rob Willoner, David Wimp: Functional design verification by multi-level simulation. 473-478
- Todd J. Wagner: Hierarchical layout verification. 484-489
- Catherine Bellon, Raoul Velazco: Taking into account asynchronous signals in functional test of complex circuits. 490-496
- Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain: A gate level model for CMOS combinational logic circuits with application to fault detection. 504-509
- Karl J. Lieberherr: Parameterized random testing. 510-516
- Stephen Y. H. Su, Tonysheng Lin: Functional testing techniques for digital LSI/VLSI systems. 517-528
- Aart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle: IDA: Interconnect delay analysis for integrated circuits. 536-541
- John K. Ousterhout: Switch-level delay models for digital MOS VLSI. 542-548
- Tsuyoshi Takahashi, Satoshi Kojima, Osamu Yamashiro, Kazuhiko Eguchi, Hideki Fukuda: An MOS digital network model on a modified thevenin equivalent for logic simulation. 549-555
- Al Dewey: The VHSIC hardware description language (VHDL) program. 556-557
- Ann R. Lanfri: Phled45: An enhanced version of caesar supporting 45° geometries. 558-564
- Masaru Ozaki, Miho Watanabe, Morio Kakinuma, Mikio Ikeda, Koji Sato: MGX: An integrated symbolic layout system for VLSI. 572-579
- Peter Marwedel: The mimola design system: Tools for the design of digital processors. 587-593
- C. L. Wardle, Charles R. Watson, C. A. Wilson, J. Craig Mudge, Bradley J. Nelson: A declarative design approach for combining macrocells by directed placement and constructive routing. 594-601
- Lawrence Snyder: A model for university, industry and government cooperation. 602-603
- J. Scott: Tutorial - mechanical workstation software computer aided engineering in the mechanical design process. 605
- Guy D. Haas: Computervision's direction in workstation technology. 606-609
- Steven Paul McCormick: EXCL: A circuit extractor for IC designs. 616-623
- John R. Dixon, Melvin K. Simmons, Paul R. Cohen: An architecture for application of artificial intelligence to design. 634-640
- Anthony S. Wojcik, Joseph Kljaich Jr., Nagendra C. E. Srinivas: A formal design verification system based on an automated reasoning system. 641-647
- Ram Banin: Hardware accelerators in the design automation environment. 648
- Anthony Zingale: The semi-custom revolution: How to thrive or survive. 649-650
- Lev A. Markov, Jeffrey R. Fox, John H. Blank: Optimization techniques for two-dimensional placement. 652-654
- Krzysztof Kozminski, Edwin Kinnen: An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits. 655-656
- Bou Nin Tien, B. S. Ting, J. Cheam, Kenneth S. K. Chow, Scott C. Evans: GALA - an automatic layout system for high density CMOS gate arrays. 657-662
- Tokinori Kozawa, Chihei Miura, Hidekazu Terai: Combine and top down block placement algorithm for hierarchical logic VLSI layout. 667-669
- John P. Blanks: Initial placement of gate arrays using least-squares methods. 670-671
- Jack A. Hudson, John A. Wisniewski, Randy C. Peters: Module positioning algorithms for rectilinear macrocell assemblies. 672-675
- John D. Crawford: An electronic design interchange format. 683-685
- V. Ashok, Walter Lee McKnight, Jayashree Ramanathan: Uniform support for information handling and problem solving required by the VLSI design process. 694-696
- Stephen Trimberger: VTIcompose - a powerful graphical chip assembly tool. 697-698
- Nripendra N. Biswas: Computer aided minimization procedure for boolean functions. 699-702
- Andrzej Wieclawski, Marek A. Perkowski: Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler. 703-704
- Ola A. Marvik: A method for IC layout verification. 708-709
- Sarma Sastry, Alice C. Parker: On the relation between wire length distributions and placement of logic on master slice ICs. 710-711
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-19T203413 by the dblp team