38. DAC 2001: Las Vegas, Nevada, USA

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Nanometer Futures

System-Level Configurability: Bus, Interface, and Processor Design

Making Verification More Efficient

SoC and High-Level DFT

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Design for Subwavelength Manufacturability: Impact on EDA

New Ideas in Logic Synthesis

Analog Design and Modeling

Scan-Based Testing

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Configurable Computing: Reconfiguring the Industry

Interconnect Design Optimization

Power Estimation Techniques

Functional Validation Based on Boolean Reasoning (BDD, SAT)

Verification: Life Beyond Algorithms

Dissecting an Embedded System: Lessons from Bluetooth

Algorithmic and Compiler Transformations for High-Level Synthesis

Gate Delay Calculation

Memory, Bus and Current Testing

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Inductance 101 and Beyond

Memory Optimization Techniques for DSP Processors

Technology Dependant Logic Synthesis

Collaborative and Distributed Design Frameworks

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Closing the Gap Between ASIC and Custom: Design Examples

Energy and Flexibility Driven Scheduling

Representation and Optimization for Digital Arithmetic Circuits

Techniques for IP Protection

Visualization and Animation for VLSI Design

Application-Specific Customization for Systems-on-a-Chip

Satisfiability Solvers and Techniques

Power and Interconnect Analysis

Domain Specific Design Methodologies

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Analysis and Implementation for Embedded Systems

Industrial Case Studies in Verification

Integrated High-Level Synthesis Based Solutions

Timing Verification and Simulation

On-Chip Communication Architectures

Compiler and Architecture Interactions

Timing with Crosstalk

Low Power Design: Systems to Interconnect

Floorplanning Representations and Placement Algorithms

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Signal Integrity: Avoidance and Test Techniques

Novel Approaches to Microprocessor Design and Verification

Scheduling Techniques for Power Management

Novel Devices and Yield Optimization