39. DAC 2002:
New Orleans, LA, USA
Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002.
ACM 2002, ISBN 1-58113-461-4
Wall street evaluates EDA
Web and IP based design
Design innovations for embedded processors
Passive model order reduction
New perspectives in physical design
Tools or Users:
Which is the Bigger Bottleneck?
Life after CMOS:
Imminent or Irrelevant?
- George Sery, Shekhar Borkar, Vivek De:
Life is CMOS: why chase the life after?
- H. Bernhard Pogge:
The next chip challenge: effective methods for viable mixed technology SoCs.
- Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier:
Few electron devices: towards hybrid CMOS-SET integrated circuits.
- R. Martel, V. Derycke, J. Appenzeller, Shalom J. Wind, Ph. Avouris:
Carbon nanotube field-effect transistors and logic circuits.
High level specification and design
- Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng:
RTL c-based methodology for designing and verifying a multi-threaded processor.
- Marcio T. Oliveira, Alan J. Hu:
High-Level specification and automatic generation of IP interface monitors.
- Kerstin Eder, Geoff Barrett:
Achieving maximum performance: a method for the verification of interlocked pipeline control logic.
- Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee:
Formal verification of module interfaces against real time specifications.
Analog Intellectual Property:
Now? Or Never?
Low-power system design
Fabric-driven logic synthesis
Memory management and address optimization in embedded systems
lighting the way to EDA riches?
What Hurts Next...?
Novel DFT, BIST and diagnosis techniques
Case studies in embedded system design
Theoretical foundations of embedded system design
Whither (or Wither?) ASIC Handoff
Embedded software automation:
from specification to binary
Applications of reconfigurable computing
New test methods targeting non-classical faults
- Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey:
Embedded software-based self-testing for SoC design.
- Swarup Bhunia, Kaushik Roy, Jaume Segura:
A novel wavelet transform based transient current analysis for fault detection and localization.
- Amir Attarha, Mehrdad Nourani:
Signal integrity fault analysis using reduced-order modeling.
- Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
How Do You Design a 10M Gate ASIC?
- Christian Berthet:
Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry.
Power distribution issues
- Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery.
- Srinivas Bodapati, Farid N. Najm:
High-level current macro-model for power-grid analysis.
- Brian W. Amick, Claude R. Gauthier, Dean Liu:
Macro-modeling concepts for the chip electrical interface.
- Hui Zheng, Lawrence T. Pileggi:
Modeling and analysis of regular symmetrically structured power/ground distribution networks.
- Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Advances in synthesis
Analog synthesis & design methodology
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits.
- Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley:
Remembrance of circuits past: macromodeling by data mining in large analog design spaces.
- Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen:
Optimal design of delta-sigma ADCs by design space exploration.
- Jan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen:
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter.
Low-power physical design
Unified Tools for SoC Embedded Systems:
Mission Critical, Mission Impossible or Mission Irrelevant?
Multi-voltage, multi-threshold design
- Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi:
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.
- Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
- Dong-In Kang, Jinwoo Suh, Stephen P. Crago:
An optimal voltage synthesis technique for a power-efficient satellite application.
Advanced simulation techniques
- Michael H. Perrott:
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.
- Baolin Yang, Joel R. Phillips:
Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method.
- Jaijeet S. Roychowdhury:
A time-domain RF steady-state method for closely spaced tones.
- Giorgio Casinovi:
An algorithm for frequency-domain noise analysis in nonlinear systems.
Design methodologies meet network applications
Advances in analog modeling
Advances in timing and simulation
Formal Verification Methods:
Getting around the Brick Wall
Routing and buffering
System on chip design
Timing analysis and memory optimization for embedded systems
Processors and accelerators for embedded applications
What's the Next EDA Driver?
Cross-talk noise analysis and management
Test cost reduction for SOCS
Scheduling techniques for embedded systems
Designing SoCs for yield improvement
Advances in SAT
- Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
A proof engine approach to solving combinational design automation problems.
- Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult SAT instances in the presence of symmetry.
- Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched?
- Slawomir Pilarski, Gracia Hu:
SAT with partial clauses and back-leaps.
- Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik:
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.
Inductance and substrate analysis
Development of processors and communication networks for embedded systems
- Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass:
System design methodologies for a wireless security processing platform.
- Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Constraint-driven communication synthesis.
- Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava:
Component-based design approach for multicore SoCs.
- Girish Varatkar, Radu Marculescu:
Traffic analysis for on-chip networks design of multimedia applications.
Moving towards more effective validation
Energy efficient mobile computing
Floorplanning and placement
- Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.
- Xiaoping Tang, D. F. Wong:
Floorplanning with alignment and performance constraints.
- Ke Zhong, Shantanu Dutt:
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control.
Circuit effects in static timing
Design space exploration for embedded systems
- Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli:
A framework for evaluating design tradeoffs in packet processing architectures.
- Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon:
Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
- Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang:
Energy exploration and reduction of SDRAM memory systems.
Last update Wed May 22 23:11:21 2013
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- Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem:
Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
- Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak:
Forward-looking objective functions: concept & applications in high level synthesis.
- Farinaz Koushanfar, Jennifer L. Wong, Jessica Feng, Miodrag Potkonjak:
ILP-based engineering change.