• 
  Sharad Malik, Limor Fix, Andrew B. Kahng (Eds.): Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004. ACM 2004 ISBN 1-58113-828-8

Panel

• 
  Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines: EDA: this is serious business. 1

Hot Leakage

• 
  Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De: Design optimizations for microprocessors at low temperature. 2-5
• 
  Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. 6-11
• 
  Lei He, Weiping Liao, Mircea R. Stan: System level leakage reduction considering the interdependence of temperature and leakage. 12-17

Clock Routing and Buffering

• 
  Anand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via cross links. 18-23
• 
  Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. 24-29
• 
  Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? 30-35

Tools and Strategies for Dynamic Verification

• 
  Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov: Industrial experience with test generation languages for processor verification. 36-40
• 
  Sigal Asaf, Eitan Marcus, Avi Ziv: Defining coverage views to improve functional coverage analysis. 41-44
• 
  Young-Su Kwon, Young-Il Kim, Chong-Min Kyung: Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. 45-48
• 
  Shai Fine, Shmuel Ur, Avi Ziv: Probabilistic regression suites for functional verification. 49-54

Timing-Driven System Synthesis

• 
  Daniel L. Rosenband, Arvind: Modular scheduling of guarded atomic actions. 55-60
• 
  Kai Kapp, Viktor K. Sabelfeld: Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis. 61-66
• 
  Fan Mo, Robert K. Brayton: A timing-driven module-based chip design flow. 67-70
• 
  Anders Edman, Christer Svensson: Timing closure through a globally synchronous, timing partitioned design methodology. 71-74

Reliable System-on-a-chip Design in the Nanometer Era

• 
  Shekhar Borkar, Tanay Karnik, Vivek De: Design and reliability challenges in nanometer technologies. 75
• 
  Naresh R. Shanbhag: A communication-theoretic design paradigm for reliable SOCs. 76
• 
  Giovanni De Micheli: Reliable communication in systems on chips. 77
• 
  Todd M. Austin: Designing robust microarchitectures. 78
• 
  Ravishankar K. Iyer: Hierarchical application aware error detection and recovery. 79

Panel

• 
  Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton: When IC yield missed the target, who is at fault? 80

Power Modeling and Optimization for Embedded Systems

• 
  Chun-Gi Lyuh, Taewhan Kim: Memory access scheduling and binding considering energy minimization in multi-bank memory systems. 81-86
• 
  Jaewon Seo, Taewhan Kim, Ki-Seok Chung: Profile-based optimal intra-task voltage scheduling for hard real-time applications. 87-92
• 
  Juan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman: Requirement-based design methods for adaptive communications links. 93-98
• 
  Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha: Automated energy/performance macromodeling of embedded software. 99-102
• 
  Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. 103-106

Performance Evaluation and Run Time Support

• 
  Tobias Schüle, Klaus Schneider: Abstraction of assembler programs for symbolic worst case execution time analysis. 107-112
• 
  Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Extending the transaction level modeling approach for fast communication architecture exploration. 113-118
• 
  Javier Resano, Daniel Mozos: Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. 119-124
• 
  Mahmut T. Kandemir: LODS: locality-oriented dynamic scheduling for on-chip multiprocessors. 125-128
• 
  Carlo Brandolese, William Fornaciari, Fabio Salice: An area estimation methodology for FPGA based designs at systemc-level. 129-132

Advances in Analog Circuit and Layout Synthesis

• 
  Johan P. Vanderhaegen, Robert W. Brodersen: Automated design of operational transconductance amplifiers using reversed geometric programming. 133-138
• 
  Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi: Correct-by-construction layout-centric retargeting of large analog designs. 139-144
• 
  Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri: Fast and accurate parasitic capacitance models for layout-aware. 145-150
• 
  Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd: ORACLE: optimization with recourse of analog circuits including layout extraction. 151-154
• 
  Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. 155-158

Power Grid Design and Analysis Techniques

• 
  Kai Wang, Malgorzata Marek-Sadowska: Buffer sizing for clock power minimization subject to general skew constraints. 159-164
• 
  Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Optimal placement of power supply pads and pins. 165-170
• 
  Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. 171-176
• 
  Su-Wei Wu, Yao-Wen Chang: Efficient power/ground network analysis for power integrity-driven design methodology. 177-180
• 
  Goeran Jerke, Jens Lienig, Jürgen Scheible: Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs. 181-184

Panel

• 
  Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar: What happened to ASIC?: Go (recon)figure? 185

Methods for A Priori Feasible Layout Generation

• 
  Li-Da Huang, Martin D. F. Wong: Optical proximity correction (OPC): friendly maze routing. 186-191
• 
  Narendra V. Shenoy, Jamil Kawa, Raul Camposano: Design automation for mask programmable fabrics. 192-197
• 
  Yajun Ran, Malgorzata Marek-Sadowska: On designing via-configurable cell blocks for regular fabrics. 198-203
• 
  V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi: Routing architecture exploration for regular fabrics. 204-207
• 
  Hiroaki Yoshida, Kaushik De, Vamsi Boppana: Accurate pre-layout estimation of standard cell characteristics. 208-211

Abstraction Techniques for Functional Verification

• 
  Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang: An efficient finite-domain constraint solver for circuits. 212-217
• 
  Zaher S. Andraus, Karem A. Sakallah: Automatic abstraction and verification of verilog models. 218-223
• 
  Freddy Y. C. Mang, Pei-Hsin Ho: Abstraction refinement by controllability and cooperativeness analysis. 224-229
• 
  Yuan Lu, Mike Jorda: Verifying a gigabit ethernet switch using SMV. 230-233
• 
  Hazem I. Shehata, Mark Aagaard: A general decomposition strategy for verifying register renaming. 234-237

Memory and Network Optimization in Embedded Designs

• 
  Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias: An integrated hardware/software approach for run-time scratchpad management. 238-243
• 
  Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo: Multi-profile based code compression. 244-249
• 
  Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya: An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. 250-255
• 
  Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde: Operating-system controlled network on chip. 256-259
• 
  Jingcao Hu, Radu Marculescu: DyAD: smart routing for networks-on-chip. 260-263

Business Day Session

• 
  Ellen Sentovich, Jaswinder Ahuja, Paul Lippe, Bernie Rosenthal: Competitive strategies for the electronics industry. 264
• 
  Ellen Sentovich, Raul Camposano, Jim Douglas, Aurangzeb Khan: Business models in IP, software licensing, and services. 264

The Future of Timing Closure

• 
  David S. Kung: Timing closure for low-FO4 microprocessor design. 265-266
• 
  Paul K. Rodman: Forest vs. trees: where's the slack? 267
• 
  Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen: Efficient timing closure without timing driven placement and routing. 268-273

Panel

• 
  Francine Bacchini, Robert F. Damiano, Bob Bentley, Kurt Baty, Kevin Normoyle, Makoto Ishii, Einat Yogev: Verification: what works and what doesn't. 274

Design Space Exploration and Scheduling for Embedded Software

• 
  Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta: Leakage aware dynamic voltage scaling for real-time embedded systems. 275-280
• 
  Lukai Cai, Andreas Gerstlauer, Daniel Gajski: Retargetable profiling for rapid, early system-level design space exploration. 281-286
• 
  Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim: High level cache simulation for heterogeneous multiprocessors. 287-292

Advances in Accelerated Simulation

• 
  Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung: Communication-efficient hardware acceleration for fast functional simulation. 293-298
• 
  Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura: A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. 299-304
• 
  Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. 305-310

Design for Manufacturing

• 
  Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. 311-316
• 
  Kevin W. McCullen: Phase correct routing for alternating phase shift masks. 317-320
• 
  Puneet Gupta, Fook-Luen Heng: Toward a systematic-variation aware timing methodology. 321-326
• 
  Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. 327-330

Statistical Timing Analysis

• 
  Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan: First-order incremental block-based statistical timing analysis. 331-336
• 
  Michael Orshansky, Arnab Bandyopadhyay: Fast statistical timing analysis handling arbitrary delay correlations. 337-342
• 
  Jiayong Le, Xin Li, Lawrence T. Pileggi: STAC: statistical timing analysis with correlation. 343-348

Panel

• 
  Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane: System level design: six success stories in search of an industry. 349-350

New Ideas in Placement

• 
  Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar: Large-scale placement by grid-warping. 351-356
• 
  Andrew B. Kahng, Sherief Reda: Placement feedback: a concept and method for better min-cut placements. 357-362
• 
  Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier: Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. 363-368

Model Order Reduction and Variational Techniques for Parasitic Analysis

• 
  Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh: Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. 369-374
• 
  Janet Meiling Wang, Omar Hafiz, Jun Li: A linear fractional transform (LFT) based model for interconnect parametric uncertainty. 375-380
• 
  Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. 381-384
• 
  Luis Miguel Silveira, Joel R. Phillips: Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. 385-388

Compilation Techniques for Embedded Applications

• 
  Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee: Automatic translation of software binaries onto FPGAs. 389-394
• 
  Philip Brisk, Adam Kaplan, Majid Sarrafzadeh: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. 395-400
• 
  Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, Guangyu Chen, Mary Jane Irwin: Data compression for improving SPM behavior. 401-406

Platform-based System Design

• 
  Gary Smith: Platform based design: does it answer the entire SoC challenge? 407
• 
  Mark Hopkins: Nomadic platform approach for wireless mobile multimedia. 408
• 
  Alberto L. Sangiovanni-Vincentelli, Luca P. Carloni, Fernando De Bernardinis, Marco Sgroi: Benefits and challenges for platform-based design. 409-414
• 
  Max Baron: Trends in the use of re-configurable platforms. 415

Innovations in Logic Synthesis

• 
  David Bañeres, Jordi Cortadella, Michael Kishinevsky: A recursive paradigm to solve Boolean relations. 416-421
• 
  Nikhil Saluja, Sunil P. Khatri: A robust algorithm for approximate compatible observability don't care (CODC) computation. 422-427
• 
  Tsutomu Sasao, Munehiro Matsuura: A method to decompose multiple-output logic functions. 428-433
• 
  Kuo-Hua Wang, Jia-Hung Chen: Symmetry detection for incompletely specified functions. 434-437
• 
  Victor N. Kravets, Prabhakar Kudva: Implicit enumeration of structural changes in circuit optimization. 438-441

Yield Estimation and Optimization

• 
  Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. 442-447
• 
  Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang: A methodology to improve timing yield in the presence of process variations. 448-453
• 
  Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Novel sizing algorithm for yield improvement under process variation in nanometer technology. 454-459
• 
  Farid N. Najm, Noel Menezes: Statistical timing analysis based on a timing yield model. 460-465

High-level Techniques for Signal Processing

• 
  Abhijit K. Deb, Axel Jantsch, Johnny Öberg: System design for DSP applications in transaction level modeling paradigm. 466-471
• 
  Bin Wu, Jianwen Zhu, Farid N. Najm: An analytical approach for dynamic range estimation. 472-477
• 
  Changchun Shi, Robert W. Brodersen: Automated fixed-point data-type optimization tool for signal processing and communication systems. 478-483
• 
  Sanghamitra Roy, Prithviraj Banerjee: An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. 484-487
• 
  Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf: Synthesizing interconnect-efficient low density parity check codes. 488-491

Advanced Test Solutions

• 
  Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. 492-497
• 
  Vinay Verma, Shantanu Dutt, Vishal Suthar: Efficient on-line testing of FPGAs with provable diagnosabilities. 498-503
• 
  Wei Li, Sudhakar M. Reddy, Irith Pomeranz: On test generation for transition faults with minimized peak power dissipation. 504-509
• 
  Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski: A new state assignment technique for testing and low power. 510-513
• 
  Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel: Automatic generation of breakpoint hardware for silicon debug. 514-517

Panel

• 
  Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah: Is statistical timing statistically significant? 498

Advances in Boolean Analysis Techniques

• 
  Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov: AMUSE: a minimally-unsatisfiable subformula extractor. 518-523
• 
  Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening: A SAT-based algorithm for reparameterization in symbolic simulation. 524-529
• 
  Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov: Exploiting structure in symmetry detection for CNF. 530-534
• 
  Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi: Refining the SAT decision ordering for bounded model checking. 535-538
• 
  Demos Anastasakis, Lisa McIlwain, Slawomir Pilarski: Efficient equivalence checking with partitions and hierarchical cut-points. 539-542

Panel

• 
  Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon: Were the good old days all that good?: EDA then and now. 543

Power Optimization for Real-Time and Media-Rich Embedded Systems

• 
  Kihwan Choi, Ramakrishna Soma, Massoud Pedram: Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. 544-549
• 
  Ying Zhang, Robert P. Dick, Krishnendu Chakrabarty: Energy-aware deterministic fault tolerance in distributed real-time embedded systems. 550-555
• 
  Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. 556-561
• 
  Xiaoping Hu, Radu Marculescu: Adaptive data partitioning for ambient multimedia. 562-565
• 
  Siddharth Choudhuri, Rabi N. Mahapatra: Energy characterization of filesystems for diskless embedded systems. 566-569

Latency Tolerance and Asynchronous Design

• 
  Vidyasagar Nookala, Sachin S. Sapatnekar: A method for correcting the functionality of a wire-pipelined circuit. 570-575
• 
  Mario R. Casu, Luca Macchiarulo: A new approach to latency insensitive design. 576-581
• 
  Qinghua Liu, Malgorzata Marek-Sadowska: Pre-layout wire length and congestion estimation. 582-587
• 
  Abhijit Davare, Kelvin Lwin, Alex Kondratyev, Alberto L. Sangiovanni-Vincentelli: The best of both worlds: the efficient asynchronous implementation of synchronous specifications. 588-591
• 
  Cheoljoo Jeong, Steven M. Nowick: Fast hazard detection in combinational circuits. 592-595

New Technologies in System Design

• 
  Margarida F. Jacome, Chen He, Gustavo de Veciana, Stephen Bijansky: Defect tolerant probabilistic design paradigm for nanotechnologies. 596-601
• 
  Jason Cong, Yiping Fan, Zhiru Zhang: Architecture-level synthesis for automatic interconnect pipelining. 602-607
• 
  Samar Abdi, Daniel Gajski: Automatic generation of equivalent architecture model from functional specification. 608-613
• 
  Bo Yang, Ramesh Karri, David A. McGrew: Divide-and-concatenate: an architecture level optimization technique for universal hash functions. 614-617
• 
  Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti: Performance analysis of different arbitration algorithms of the AMBA AHB bus. 618-621

BioMEMS

• 
  Tom Korsmeyer, Jun Zeng, Ken Greiner: Design tools for BioMEMS. 622-628
• 
  Jacob White: CAD challenges in BioMEMS design. 629-632

Panel

• 
  Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser: Will Moore's Law rule in the land of analog? 633

Floorplanning

• 
  Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim: Profile-guided microarchitectural floorplanning for deep submicron processor design. 634-639
• 
  Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He: Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. 640-645
• 
  Jing Li, Tan Yan, Bo Yang, Juebang Yu, Chunhui Li: A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation. 646-651

Issues in Timing Analysis

• 
  Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm: Worst-case circuit delay taking into account power supply variations. 652-657
• 
  Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. 658-663
• 
  Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. 664-669

ISSCC Highlights

• 
  Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson: Design and implementation of the POWER5 microprocessor. 670-672
• 
  Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon: A dual-core 64b ultraSPARC microprocessor for dense server applications. 673-677
• 
  Daniel J. Deleganes, Micah Barany, George Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal Wijeratne: Low voltage swing logic circuits for a Pentium 4 processor integer core. 678-680

Multiprocessor SoC MPSoC Solutions/Nightmare

• 
  Wayne Wolf: The future of multiprocessor systems-on-chips. 681-685
• 
  Tim Kogel, Heinrich Meyr: Heterogeneous MP-SoC: the solution to energy-efficient signal processing. 686-691
• 
  Chris Rowen, Steve Leibson: Flexible architectures for engineering successful SOCs. 692-697

Timing Issues in Placement

• 
  Prashant Saxena, Bill Halpin: Modeling repeaters explicitly within analytical placement. 699-704
• 
  Bernd Obermeier, Frank M. Johannes: Quadratic placement using an improved timing model. 705-710
• 
  Milos Hrkic, John Lillis, Giancarlo Beraudo: An approach to placement-coupled logic replication. 711-716

Design Methodologies for ASIPs

• 
  Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr: A novel approach for flexible and consistent ADL-driven ASIP design. 717-722
• 
  Pan Yu, Tulika Mitra: Characterizing embedded applications for instruction-set extensible processors. 723-728
• 
  Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt: Introduction of local memory elements in instruction set extensions. 729-734

FPGA-Based Systems

• 
  Fei Li, Yan Lin, Lei He: FPGA power reduction using configurable dual-Vdd. 735-740
• 
  Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis: Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. 741-746
• 
  Nobuyuki Ohba, Kohji Takano: An SoC design methodology using FPGAs and embedded microprocessors. 747-752

Security as a New Dimension in Embedded System Design

• 
  Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan: Security as a new dimension in embedded system design. 753-760

Leakage Power Optimization

• 
  Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Tradeoffs between date oxide leakage and delay for dual T_ox circuits. 761-766
• 
  Kaviraj Chopra, Sarma B. K. Vrudhula: Implicit pseudo boolean enumeration algorithms for input vector control. 767-772
• 
  Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. 773-778
• 
  Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. 779-782
• 
  Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. 783-787

Interconnect Extraction

• 
  Shu Yan, Vivek Sarin, Weiping Shi: Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. 788-793
• 
  Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala: A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. 794-799
• 
  Satrajit Gupta, Lawrence T. Pileggi: CHIME: coupled hierarchical inductance model evaluation. 800-805
• 
  Sharad Kapur, David E. Long: Large-scale full-wave simulation. 806-809
• 
  Yuichi Tanji, Hideki Asai: Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. 810-813

New Frontiers in Logic Synthesis

• 
  Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu: Re-synthesis for delay variation tolerance. 814-819
• 
  Aiqun Cao, Cheng-Kok Koh: Post-layout logic optimization of domino circuits. 820-825
• 
  Peter Tummeltshammer, James C. Hoe, Markus Püschel: Multiple constant multiplication by time-multiplexed mapping of addition chains. 826-829
• 
  Hemangee K. Kapoor, Mark B. Josephs: Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. 830-833
• 
  Pawel Kerntopf: A new heuristic algorithm for reversible logic synthesis. 834-837
• 
  William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski: Quantum logic synthesis by symbolic reachability analysis. 838-841

Numerical Techniques for Simulation

• 
  Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi: A frequency relaxation approach for analog/RF system-level simulation. 842-847
• 
  Ting Mei, Jaijeet S. Roychowdhury, Todd S. Coffey, Scott A. Hutchinson, David M. Day: Robust, stable time-domain methods for solving MPDEs of fast/slow systems. 848-853
• 
  Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. 854-859
• 
  Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. 860-863
• 
  Baolin Yang, Bruce McGaughy: An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling. 864-867

Energy and Thermal-Aware Design

• 
  Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. 868-873
• 
  R. Reed Taylor, Herman Schmit: Enabling energy efficiency in via-patterned gate array devices. 874-878
• 
  Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy: Compact thermal modeling for temperature-aware design. 878-883
• 
  Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. 884-887

Noise-Tolerant Design and Analysis Techniques

• 
  Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum: Noise characterization of static CMOS gates. 888-893
• 
  Chong Zhao, Xiaoliang Bai, Sujit Dey: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. 894-899
• 
  Li Ding, Pinaki Mazumder: A novel technique to improve noise immunity of CMOS dynamic logic circuits. 900-903
• 
  Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. 904-907

New Tools and Methods for Future Embedded SoC

• 
  Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya: Debugging HW/SW interface for MPSoC: video encoder system design case study. 908-913
• 
  Srinivasan Murali, Giovanni De Micheli: SUNMAP: a tool for automatic topology selection and generation for NoCs. 914-919
• 
  Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. 920-923
• 
  Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle: Mapping a domain specific language to a platform FPGA. 924-927

New Scan-Based Test Techniques

• 
  Irith Pomeranz: On the generation of scan-based test sets with reachable states for testing under functional operation conditions. 928-933
• 
  Peter Wohl, John A. Waicukauski, Sanjay Patel: Scalable selector architecture for x-tolerant deterministic BIST. 934-939
• 
  Irith Pomeranz: Scan-BIST based on transition probabilities. 940-943
• 
  Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota: Combining dictionary coding and LFSR reseeding for test data compression. 944-947

CAD for Reconfigurable Computing

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  Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual memory window for application-specific reconfigurable coprocessors. 948-953
• 
  Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: Dynamic FPGA routing for just-in-time FPGA compilation. 954-959
• 
  Manish Handa, Ranga Vemuri: An efficient algorithm for finding empty space for online FPGA placement. 960-965