• 
  Ellen Sentovich (Ed.): Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006. ACM 2006 ISBN 1-59593-381-6

Session 1: Panel

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  Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu: How will the fabless model survive? 1-2

Session 2: special session: why doesn't my system work?

• 
  Doug Josephson: The good, the bad, and the ugly of silicon debug. 3-6
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  Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller: A reconfigurable design-for-debug infrastructure for SoCs. 7-12
• 
  Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang: Visibility enhancement for silicon debug. 13-18

Session 3: hierarchical synthesis for mixed-signal designs

• 
  Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: A CPPLL hierarchical optimization methodology considering jitter, power and locking time. 19-24
• 
  Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen: Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. 25-30
• 
  Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. 31-36

Session 4: processor and communication centric SOC design

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  Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino: A real time budgeting method for module-level-pipelined bus based system using bus scenarios. 37-42
• 
  Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra: Exploiting forwarding to improve data bandwidth of instruction-set extensions. 43-48
• 
  Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. 49-52
• 
  Xinping Zhu, Wei Qin: Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery. 53-56

Session 5: practical applications of DFM

• 
  Kanak Agarwal, Sani R. Nassif: Statistical analysis of SRAM cell stability. 57-62
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  Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah: Criticality computation in parameterized statistical timing. 63-68
• 
  Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif: Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. 69-72
• 
  Jie Yang, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig: An up-stream design auto-fix flow for manufacturability enhancement. 73-76

DAC technologist panel

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  G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang: "The IC nanometer race -- what will it take to win?". 77-78

Session 7: special session: bridging the system to RTL verification gap

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  David Brier, Raj S. Mitra: Use of C/C++ models for architecture exploration and verification of DSPs. 79-84
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  Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard: Maintaining consistency between systemC and RTL system designs. 85-89
• 
  Stuart Swan: SystemC transaction level models and RTL verification. 90-92
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  Philippe Georgelin, Venkat Krishnaswamy: Towards a C++-based design methodology facilitating sequential equivalence checking. 93-96

Session 8: leakage, power analysis and optimization

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  Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram: Charge recycling in MTCMOS circuits: concept and analysis. 97-102
• 
  Xin Li, Jiayong Le, Lawrence T. Pileggi: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. 103-108
• 
  Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo: Physical design methodology of power gating circuits for standard-cell-based design. 109-112
• 
  Kaijian Shi, David Howard: Challenges in sleep transistor design and implementation in low-power designs. 113-116
• 
  Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. 117-120
• 
  De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh: Timing driven power gating. 121-124

Session 9: MPSOC design methodologies and applications

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  Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. 125-130
• 
  Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: An automated, reconfigurable, low-power RFID tag. 131-136
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  Hyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang: Design space exploration and prototyping for on-chip multimedia applications. 137-142
• 
  Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen: Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. 143-148

Session 10: statistical timing analysis

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  Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Refined statistical static timing analysis through. 149-154
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  Jaskirat Singh, Sachin S. Sapatnekar: Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. 155-160
• 
  Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky: Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. 161-166
• 
  Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar: Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. 167-172
• 
  Ron Wilson, Yervant Zorian: Decision-making for complex SoCs in consumer electronic products. 173

Panel

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  A. Yang, R. Chandra, S. Burke, J. A. DeLaCruz, S. Santhanam, U. Ko: Entering the hot zone: can you handle the heat and be cool? 174-175

Session 12: Special Session: reliability challenges for 65NM and beyond

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  J. W. McPherson: Reliability challenges for 45nm and beyond. 176-181
• 
  Zhihong Liu, Bruce McGaughy, James Z. Ma: Design tools for reliability analysis. 182-187
• 
  Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar: Design in reliability for communication designs. 188-192
• 
  T. Pompl, C. Schlünder, M. Hommel, H. Nielen, J. Schneider: Practical aspects of reliability analysis for IC designs. 193-198

Session 13: power grid analysis and design

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  Sanjay Pant, Eli Chiprout: Power grid physics and implications for CAD. 199-204
• 
  Hao Yu, Yiyu Shi, Lei He: Fast analysis of structured power grid by triangularization based structure preserving model order reduction. 205-210
• 
  Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda: Stochastic variational analysis of large power grids considering intra-die correlations. 211-216
• 
  Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. 217-222

Session 14: advances in formal solvers

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  Ziv Nevo, Monica Farkash: Distributed dynamic BDD reordering. 223-228
• 
  Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli: SAT sweeping with local observability don't-cares. 229-234
• 
  Chao Wang, Aarti Gupta, Malay K. Ganai: Predicate learning and selective theory deduction for a difference logic solver. 235-240
• 
  Vishnu C. Vimjam, Michael S. Hsiao: Fast illegal state identification for improving SAT-based induction. 241-246

Session 15: gate modeling and model order reduction

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  Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout: A multi-port current source model for multiple-input switching effects in CMOS library cells. 247-252
• 
  Hanif Fatemi, Shahin Nazarian, Massoud Pedram: Statistical logic cell delay analysis using a current-based model. 253-256
• 
  Ngai Wong, Venkataramanan Balakrishnan: Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation. 257-260
• 
  N. Wong, C. K. Chu: A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils. 261-266
• 
  Peng Li, Weiping Shi: Model order reduction of linear networks with massive ports via frequency-dependent port packing. 267-272
• 
  Nic Mokhoff, Yervant Zorian: Tradeoffs and choices for emerging SoCs in high-end applications. 273

Session 16: special session: MPSOC design tools

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  Grant Martin: Overview of the MPSoC design challenge. 274-279
• 
  Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot: Programming models and HW-SW interfaces abstraction for multi-processor SoC. 280-285
• 
  Peter Flake, Simon J. Davidmann, Frank Schirrmeister: System-level exploration tools for MPSoC designs. 286-287

Session 17: special session - highlights of ISSCC: multimedia

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  Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang: Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. 288-289
• 
  Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho: A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. 290-291
• 
  Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno: Hierarchical power distribution and power management scheme for a single chip mobile processor. 292-295

Session 18: buffer insertion

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  Mandar Waghmode, Zhuo Li, Weiping Shi: Buffer insertion in large circuits with constructive solution search techniques. 296-301
• 
  Yuantao Peng, Xun Liu: Low-power repeater insertion with both delay and slew rate constraints. 302-307
• 
  Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. 308-313

Session 19: testing and validation for timing defects

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  Vikram Iyengar, Gary Grise, Mark Taylor: A flexible and scalable methodology for GHz-speed structural test. 314-319
• 
  Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Timing-based delay test for screening small delay defects. 320-325
• 
  Amitava Majumdar, Wei-Yu Chen, Jun Guo: Hold time validation on silicon and the relevance of hazards in timing analysis. 326-331

Session 20: advanced topics in processor and system verification

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  Alon Gluska: Practical methods in coverage-oriented verification of the merom microprocessor. 332-337
• 
  Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson: Verification of the cell broadband engine^TM processor. 338-343
• 
  Ilya Wagner, Valeria Bertacco, Todd M. Austin: Shielding against design flaws with field repairable control logic. 344-347
• 
  Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen: Scheduling-based test-case generation for verification of multimedia SoCs. 348-351

Session 21: software for real-time applications

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  Xiangrong Zhou, Peter Petrov: Rapid and low-cost context-switch through embedded processor customization for real-time and control applications. 352-357
• 
  Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen: Efficient detection and exploitation of infeasible paths for software timing analysis. 358-363
• 
  Po-Kuan Huang, Soheil Ghiasi: Leakage-aware intraprogram voltage scaling for embedded processors. 364-369

Session 22: panel

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  Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch: Building a standard ESL design and verification methodology: is it just a dream? 370-371

Session 23: invited session

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  Andrew B. Kahng: CAD challenges for leading-edge multimedia designs. 372

Session 24: routing

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  Minsik Cho, David Z. Pan: BoxRouter: a new global router based on box expansion and progressive ILP. 373-378
• 
  Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. 379-384
• 
  Yiyu Shi, Paul Mesa, Hao Yu, Lei He: Circuit simulation based obstacle-aware Steiner routing. 385-388
• 
  Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang: Timing-driven Steiner trees are (practically) free. 389-392

Session 25: the test bin

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  Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic software-based self-test for pipelined processors. 393-398
• 
  Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: A test pattern ordering algorithm for diagnosis with truncated fail data. 399-404
• 
  Ahmad A. Al-Yamani: DFT for controlled-impedance I/O buffers. 405-410

Session 26: panel

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  Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? 411-412

Session 27: low power and ultra-low voltage design

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  Hari Ananthan, Kaushik Roy: A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. 413-418
• 
  Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. 419-424
• 
  John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. 425-428
• 
  Huaizhi Wu, Martin D. F. Wong, I-Min Liu: Timing-constrained and voltage-island-aware voltage assignment. 429-432

Session 28: high-level exploration and optimization

• 
  Jason Cong, Zhiru Zhang: An efficient and versatile scheduling algorithm based on SDC formulation. 433-438
• 
  Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu: Register binding for clock period minimization. 439-444
• 
  Ajay K. Verma, Paolo Ienne: Towards the automatic exploration of arithmetic-circuit architectures. 445-450
• 
  Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner: Design space exploration using time and resource duality with the ant colony optimization. 451-454
• 
  Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda: Rapid estimation of control delay from high-level specifications. 455-458

Session 29: panel design challenges for next-generation multimedia, game and entertainment platforms

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  John M. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, B. Traw: Design challenges for next-generation multimedia, game and entertainment platforms. 459

Session 30: CAD for FPGAS

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  Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi: Architecture-aware FPGA placement using metric embedding. 460-465
• 
  Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. 466-471
• 
  Joey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. 472-477
• 
  Yu Hu, Yan Lin, Lei He, Tim Tuan: Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. 478-483

Session 31: secure systems

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  Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro: VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals. 484-489
• 
  Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang: A network security processor design based on an integrated SOC design and test platform. 490-495
• 
  Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. 496-501
• 
  Roshan G. Ragel, Sri Parameswaran: IMPRES: integrated monitoring for processor reliability and security. 502-505
• 
  Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez: A parallelized way to provide data encryption and integrity checking on a processor-memory bus. 506-509

Session 32: logic synthesis I

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  Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. 510-515
• 
  Kuo-Hua Wang: Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection. 516-521
• 
  Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. 522-527
• 
  Brian Swahn, Soha Hassoun: Gate sizing: finFETs vs 32nm bulk MOSFETs. 528-531
• 
  Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: DAG-aware AIG rewriting a fresh look at combinational logic synthesis. 532-535

Session 33: low-power, thermal-aware architectures

• 
  Björn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd Vandersteen, Francky Catthoor: Energy-scalable OFDM transmitter design and control. 536-541
• 
  Rajarshi Mukherjee, Seda Ogrenci Memik: Systematic temperature sensor allocation and placement for microprocessors. 542-547
• 
  Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha: HybDTM: a coordinated hardware-software approach for dynamic thermal management. 548-553
• 
  Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: A systematic method for functional unit power estimation in microprocessors. 554-557
• 
  Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. 558-561

Session 34: low power system level design

• 
  Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula: Extending the lifetime of fuel cell based hybrid systems. 562-567
• 
  Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula: High-level power management of embedded systems with application-specific energy cost functions. 568-573
• 
  Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng: Communication latency aware low power NoC synthesis. 574-579
• 
  Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. 580-585

Session 35: power-constrained design for multimedia

• 
  Lin Zhong, Bin Wei, Michael J. Sinclair: SMERT: energy-efficient design of a multimedia messaging system for mobile devices. 586-591
• 
  Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu: Signature-based workload estimation for mobile 3D graphics. 592-597
• 
  Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi: Games are up for DVFS. 598-603
• 
  Ali Iranli, Wonbok Lee, Massoud Pedram: Backlight dimming in power-aware mobile displays. 604-607
• 
  Wei-Chung Cheng, Chain-Fu Chao: Minimization for LED-backlit TFT-LCDs. 608-611

Session 36: electrical and thermal issues in FPGAS

• 
  Yan Meng, Timothy Sherwood, Ryan Kastner: Leakage power reduction of embedded memories on FPGAs through location assignment. 612-617
• 
  David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. 618-623
• 
  Georges Nabaa, Navid Azizi, Farid N. Najm: An adaptive FPGA architecture with process variation compensation and reduced leakage. 624-629
• 
  Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. 630-635

Session 37: special session: beyond low-power design: environmental energy harvesting

• 
  Dean D. MacNeil, Edward H. Sargent: Solution-processed infrared photovoltaic devices. 636-638
• 
  Rajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou: Circuits for energy harvesting sensor signal processing. 639-644
• 
  Joseph A. Paradiso: Systems for human-powered mobile computing. 645-650
• 
  Aman Kansal, Jason Hsu, Mani B. Srivastava, Vijay Raghunathan: Harvesting aware power management for sensor networks. 651-656

Session 38: communication-driven synthesis

• 
  Jordi Cortadella, Michael Kishinevsky, Bill Grundmann: Synthesis of synchronous elastic architectures. 657-662
• 
  Sujan Pandey, Manfred Glesner: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. 663-668
• 
  Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. 669-674
• 
  Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang: Behavior and communication co-optimization for systems with sequential communication media. 675-678
• 
  Cristian Soviani, Ilija Hadzic, Stephen A. Edwards: Synthesis of high-performance packet processing pipelines. 679-682

Session 39: parallelism and memory optimizations

• 
  Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya: Buffer memory optimization for video codec application modeled in Simulink. 689-694
• 
  Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid: Configurable cache subsetting for fast cache tuning. 695-700
• 
  Lei Yang, Haris Lekatsas, Robert P. Dick: High-performance operating system controlled memory compression. 701-704
• 
  Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. 705-708
• 
  Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir: Optimizing code parallelization through a constraint network based approach. 863-688

Session 40: panel

• 
  Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini: Tomorrow's analog: just dead or just different? 709-710

Session 41: nanotubes and nanowires

• 
  Wei Zhang, Niraj K. Jha, Li Shang: NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. 711-716
• 
  Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee: Modeling and analysis of circuit performance of ballistic CNFET. 717-722
• 
  Wenjing Rao, Alex Orailoglu, Ramesh Karri: Topology aware mapping of logic functions onto nanowire-based crossbar architectures. 723-726
• 
  Reza M. Rad, Mohammad Tehranipoor: A new hybrid FPGA with nanoscale clusters and CMOS routing. 727-730

Session 42: simulation assisted formal verification

• 
  Saurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra: Directed-simulation assisted formal verification of serial protocol and bridge. 731-736
• 
  Kuntal Nanshi, Fabio Somenzi: Guiding simulation with increasingly refined abstract traces. 737-742
• 
  Weixin Wu, Michael S. Hsiao: Mining global constraints for improving bounded sequential equivalence checking. 743-748

Session 43: yield analysis and improvement

• 
  Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang: An IC manufacturing yield model considering intra-die variations. 749-754
• 
  Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Novel full-chip gridless routing considering double-via insertion. 755-760
• 
  Jia Wang, Hai Zhou: Optimal jumper insertion for antenna avoidance under ratio upper-bound. 761-766

Session 44: approaches to soft error mitigation

• 
  Natasa Miskov-Zivanov, Diana Marculescu: MARS-C: modeling and reduction of soft errors in combinational circuits. 767-772
• 
  Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. 773-778
• 
  Navid Azizi, Farid N. Najm: A family of cells to reduce the soft-error-rate in ternary-CAM. 779-784

Session 45: design/technology interaction

• 
  Peng Yu, Sean X. Shi, David Z. Pan: Process variation aware OPC with variational lithography modeling. 785-790
• 
  Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. 791-796
• 
  Frank Huebbers, Ali Dasdan, Yehea I. Ismail: Computation of accurate interconnect process parameter values for performance corners under process variations. 797-800
• 
  Ke Cao, Sorin Dobre, Jiang Hu: Standard cell characterization considering lithography induced variations. 801-804

Session 46: panel

• 
  J. Bergeron, H. Foster, A. Piziali, R. S. Mitra, Catherine Ahlschlager, D. Stein: Building a verification test plan: trading brute force for finesse. 805-806

Session 47: special session: more Moore's law and more than Moore's law

• 
  Shekhar Borkar: Electronics beyond nano-scale CMOS. 807-808
• 
  Kaustav Banerjee, Navin Srivastava: Are carbon nanotubes the future of VLSI interconnections? 809-814
• 
  Erwin J. Prinz: The zen of nonvolatile memories. 815-820

Session 48: formal specification and verification testbench generation

• 
  Ingo Pill, Simone Semprini, Roberto Cavada, Marco Roveri, Roderick Bloem, Alessandro Cimatti: Formal analysis of hardware requirements. 821-826
• 
  Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta: Test generation games from formal specifications. 827-832

Session 49: analysis and optimization issues in NoC design

• 
  Lap-Fai Leung, Chi-Ying Tsui: Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems. 833-838
• 
  Ümit Y. Ogras, Radu Marculescu: Prediction-based flow control for network-on-chip traffic. 839-844
• 
  Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. 845-848
• 
  Ming Li, Qing-An Zeng, Wen-Ben Jone: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. 849-852

Session 50: special session: key technologies for beyond the die

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  Kaushik Sheth, Egino Sarto, Joel McGrath: The importance of adopting a package-aware chip design flow. 853-856
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  Chirag S. Patel: Silicon carrier for computer systems. 857-862
• 
  Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann: 4.25 Gb/s laser driver: design challenges and EDA tool limitations. 863-866
• 
  Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang: Power-centric design of high-speed I/Os. 867-872

Session 51: analog design and design assistance

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  Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni: A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. 873-878
• 
  Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers. 879-884
• 
  Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein: Chameleon ART: a non-optimization based analog design migration framework. 885-888
• 
  Michaël Goffioul, Gerd Vandersteen, Joris Van Driessche, Björn Debaillie, Boris Come: Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP. 889-892

Session 52: high-performance simulation of transaction level and dataflow models

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  Chia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya: Efficient simulation of critical synchronous dataflow graphs. 893-898
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  Sander Stuijk, Marc Geilen, Twan Basten: Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. 899-904
• 
  Wolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton: GreenBus: a generic interconnect fabric for transaction level modelling. 905-910
• 
  Fernando Herrera, Eugenio Villar: A framework for embedded system specification under different models of computation in SystemC. 911-914
• 
  Elvinia Riccobene, Patrizia Scandurra, Alberto Rosti, Sara Bocchio: A model-driven design environment for embedded systems. 915-918

Session 53: nano- and bio-chip design

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  Constantin Pistol, Alvin R. Lebeck, Chris Dwyer: Design automation for DNA self-assembled nanostructures. 919-924
• 
  William L. Hwang, Fei Su, Krishnendu Chakrabarty: Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*. 925-930
• 
  Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of digital microfluidic biochips using the t-tree formulation. 931-934
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  Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. 935-938

Session 54: logic and sequential synthesis

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  Josep Carmona, Jordi Cortadella: State encoding of large asynchronous controllers. 939-944
• 
  Chuan Lin, Hai Zhou: An efficient retiming algorithm under setup and hold constraints. 945-950
• 
  Kui Wang, Lian Duan, Xu Cheng: ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling. 951-954
• 
  Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa: Budgeting-free hierarchical design method for large scale and high-performance LSIs. 955-958
• 
  Azadeh Davoodi, Ankur Srivastava: Variability driven gate sizing for binning yield optimization. 959-964

Session 55: low power circuit design

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  Quming Zhou, Kartik Mohanram: Elmore model for energy estimation in RC trees. 965-970
• 
  Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. 971-976
• 
  Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. 977-982
• 
  Saumil Shah, Puneet Gupta, Andrew B. Kahng: Standard cell library optimization for leakage reduction. 983-986
• 
  Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu: Low-power bus encoding using an adaptive hybrid algorithm. 987-990

Session 56: beyond-the-die circuit and system integration

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  Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. 991-996
• 
  Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis: Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. 997-1002
• 
  Rui Shi, Chung-Kuan Cheng: Efficient escape routing for hexagonal array of high density I/Os. 1003-1008
• 
  Rohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, Madhavan Swaminathan: System level signal and power integrity analysis methodology for system-in-package applications. 1009-1012
• 
  William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel: PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. 1013-1016

Session 57: new ideas in analog/RF modeling and simulation

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  Xiaolue Lai, Jaijeet S. Roychowdhury: A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators. 1017-1022
• 
  Ying Wei, Alex Doboli: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling. 1023-1028
• 
  Ting Mei, Jaijeet S. Roychowdhury: A robust envelope following method applicable to both non-autonomous and oscillatory circuits. 1029-1034
• 
  Guo Yu, Peng Li: Lookup table based simulation and statistical modeling of Sigma-Delta ADCs. 1035-1040

Session 58: advanced methods for interconnect extraction, clocks and reliability

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  Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock buffer and wire sizing using sequential programming. 1041-1046
• 
  Rakesh Vattikonda, Wenping Wang, Yu Cao: Modeling and minimization of PMOS NBTI effect for robust nanometer design. 1047-1052
• 
  Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala: A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures. 1053-1056
• 
  Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. 1057-1060

Session 59: panel

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  Shishpal Rawat, Raul Camposano, A. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, A. Sharan: DFM: where's the proof of value? 1061-1062

Session 60: bounded model checking and equivalence verification

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  Xiushan Feng, Alan J. Hu: Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification. 1063-1068
• 
  Guy Dupenloup, Thierry Lemeunier, Roland Mayr: Transistor abstraction for the functional verification of FPGAs. 1069-1072
• 
  Mohammad Awedh, Fabio Somenzi: Automatic invariant strengthening to prove properties in bounded model checking. 1073-1076
• 
  Prakash Mohan Peranandam, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel: Fast falsification based on symbolic bounded property checking. 1077-1082

Session 61: test response compaction and ATPG

• 
  Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei: Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. 1083-1088
• 
  Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Test response compactor with programmable selector. 1089-1094
• 
  Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke: Fault detection and diagnosis with parity trees for space compaction of test responses. 1095-1098
• 
  Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton: Multiple-detect ATPG based on physical neighborhoods. 1099-1102

Session 62: placement

• 
  Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack: Constraint-driven floorplan repair. 1103-1108
• 
  Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu: Optimal cell flipping in placement and floorplanning. 1109-1114
• 
  Tao Luo, David Newmark, David Z. Pan: A new LP based incremental timing driven placement for high performance designs. 1115-1120