30. DAC 1993: Dallas, Texas, USA

Asynchronous Circuit Design

• Tam Anh Chu, Narayana Mani, Clement K. C. Leung:
  An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines. 2-6
  
• Cho W. Moon, Robert K. Brayton:
  Elimination of Dynamic hazards by Factoring. 7-13
  

Sequential Circuit Analysis and Optimization

• Régis Leveugle:
  Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. 14-18
  
• Alice M. Tokarnia:
  Minimal Shift Counters and Frequency Division. 19-24
  
• Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi:
  Algorithms for Approximate FSM Traversal. 25-30
  

Fast Algorithm for Layout Analysis

• Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather:
  SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. 31-37
  
• Lorenz Ladage, Rainer Leupers:
  Resistance Extraction using a Routing Algorithm. 38-42
  
• Glenn G. Lai, Donald S. Fussell, D. F. Wong:
  HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. 43-47
  

Increasing Design Quality and Engineering Productivity through Design Reuse

• Emil F. Girczyc, Steve Carlson:
  Increasing Design Quality and Engineering Productivity through Design Reuse. 48-53
  

New Ideas in Technology Mapping

• Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang:
  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. 54-60
  
• Polly Siegel, Giovanni De Micheli, David L. Dill:
  Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. 61-67
  
• Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain:
  Technology Decomposition and Mapping Targeting Low Power Dissipation. 68-73
  
• Vivek Tiwari, Pranav Ashar, Sharad Malik:
  Technology Mapping for Lower Power. 74-79
  

Test Generation

• Irith Pomeranz, Sudhakar M. Reddy:
  INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. 80-85
  
• Kwang-Ting Cheng, A. S. Krishnakumar:
  Automatic Functional Test Generation Using the Extended Finite State Machine Model. 86-91
  
• Jean François Santucci, Anne-Lise Courbis, Norbert Giambiasi:
  Speed up of Behavioral A.T.P.G. using a Heuristic Criterion. 92-96
  
• Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin:
  A State Traversal Algorithm Using a State Covariance Matrix. 97-101
  
• Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
  Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. 102-106
  
• Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo:
  Sequential Circuit Test Generation on a Distributed System. 107-111
  

Timing Estimation and Verification

• Hoon Chang, Jacob A. Abraham:
  VIPER: An Efficient Vigorously Sensitizable Path Extractor. 112-117
  
• Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
  A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem. 118-122
  
• Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli:
  A Verification Technique for Gated Clock. 123-127
  
• William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. 128-134
  
• Wen-Ben Jone, Chen-Liang Fang:
  Timing Optimization By Gate Resizing And Critical Path Identification. 135-140
  

Panel

• Kurt Keutzer:
  What is the Next Big Productivity Boost for Designers? (Panel Abstract). 141
  

Optimization of Analog Circuits

• Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich:
  Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. 142-147
  
• N. S. Nagaraj:
  A New Optimizer for Performance Optimization of Analog Integrated Circuits. 148-153
  
• Abhijit Dharchoudhury, Sung-Mo Kang:
  Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. 154-158
  
• Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli:
  Analog System Verification in the Presence of Parasitics Using Behavioral Simulation. 159-163
  

Panel

• Jonathan Rose:
  Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). 164
  

Optimal Tree Construction

• Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage:
  Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. 165-170
  
• Andrew Lim, Siu-Wing Cheng, Ching-Ting Wu:
  Performance Oriented Rectilinear Steiner Trees. 171-176
  
• Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang:
  Performance-Driven Steiner Tree Algorithm for Global Routing. 177-181
  
• Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins:
  High-Performance Routing Trees With Identified Critical Sinks. 182-187
  

High Level Design Implementation

• Ing-Yi Chen, Geng-Lin Chen, Fredrick J. Hill, Sy-Yen Kuo:
  The Sea-of-Wires Array Aynthesis System. 188-193
  
• Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru:
  Experiences in Functional Validation of a High Level Synthesis System. 194-201
  
• Nam Sung Woo, Jaeseok Kim:
  An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.. 202-207
  

Technology Mapping for FPGAS and Layout

• Prashant Sawkar, Donald E. Thomas:
  Performance Directed Technology Mapping for Look-Up Table Based FPGAs. 208-212
  
• Jason Cong, Yuzheng Ding:
  On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. 213-218
  
• Mahesh Mehendale:
  MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. 219-223
  
• Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Sequential Synthesis for Table Look Up Programmable Gate Arrays. 224-229
  
• Hirendu Vaishnav, Massoud Pedram:
  Routability-Driven Fanout Optimization. 230-235
  

Design for Test

• Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel:
  Non-Scan Design-for-Testability Techniques for Sequential Circuits. 236-241
  
• Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
  An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. 242-248
  
• Dimitrios Kagaris, Spyros Tragoudas:
  Partial Scan with Retiming. 249-254
  
• Prashant S. Parikh, Miron Abramovici:
  A Cost-Based Approach to Partial Scan. 255-259
  

Extending the Applicability of BDDs

• Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton:
  On Computing the Transitive Closure of a State Transition Relation. 260-265
  
• Alan J. Hu, David L. Dill:
  Reducing BDD Size by Exploiting Functional Dependencies. 266-271
  
• Shin-ichi Minato:
  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems. 272-277
  

Information Modeling

• Rachel Y. W. Lau, Hilary J. Kahn:
  Information Modelling of EDIF. 278-283
  

Panel

• Stephen R. Pollock:
  Life Expectancy of Standards (Panel Abstract). 284
  

System Implementation Issues

• Mehrdad Nourani, Christos A. Papachristou:
  A Layout Estimation Algorithm for RTL Datapaths. 285-291
  
• Tien-Chien Lee, Niraj K. Jha, Wayne Wolf:
  Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. 292-297
  
• Taewhan Kim, C. L. Liu:
  Utilization of Multiport Memories in Data Path Synthesis. 298-302
  
• Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy:
  Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. 303-307
  

Panel

• Wayne Wolf:
  Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box? (Panel Abstract). 308
  

FPGA Layout and Partitioning

• Rajmohan Rajaraman, D. F. Wong:
  Optimal Clustering for Delay Minimization. 309-314
  
• Roman Kuznar, Franc Brglez, Krzysztof Kozminski:
  Cost Minimization of Partitions into Multiple Devices. 315-320
  
• Sudip Nag, Kaushik Roy:
  Iterative Wirability and Performance Improvement for FPGAs. 321-325
  
• Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
  On Routability Prediction for Field-Programmable Gate Arrays. 326-330
  

EDAC User Session

• Ralph D. Nurnberger:
  The Clinton/Gore Technology Policies. 331-335
  

DSP Synthesis

• Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu:
  High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. 336-342
  
• Abhijit Chatterjee, Rabindra K. Roy:
  An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. 343-348
  
• Alok Sharma, Rajiv Jain:
  InSyn: Integrated Scheduling for DSP Applications. 349-354
  
• Alok Sharma, Rajiv Jain:
  Estimating Architectural Resources and Performance for High-Level Synthesis Applications. 355-360
  

Simulation and Analysis of Digital Circuits

• Bradley S. Carlson, C. Y. Roger Chen:
  Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. 361-366
  
• Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh:
  Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. 367-372
  
• Benoit A. Gennart:
  Comparative Design Validation Based on Event Pattern Mappings. 373-378
  
• Georgios I. Stamoulis, Ibrahim N. Hajj:
  Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. 379-383
  
• Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj:
  Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. 384-388
  

Large-Scale Compaction

• Cyrus Bamji, Ravi Varadarajan:
  MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. 389-394
  
• So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
  Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. 395-400
  
• Peichen Pan, Sai-keung Dong, C. L. Liu:
  Optimal Graph Constraint Reduction for Symbolic Layout Compaction. 401-406
  
• Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori:
  A Compaction Method for Full Chip VLSI Layouts. 407-412
  

Issues in System Design

• Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran:
  High-Level Transformations for Minimizing Syntactic Variances. 413-418
  
• Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani:
  An Approach for Redesigning in Data Path Synthesis. 419-423
  
• Andrew Seawright, Forrest Brewer:
  High-Level Symbolic Construction Technique for High Performance Sequential Synthesis. 424-428
  
• Ramesh Karri, Alex Orailoglu:
  High-Level Synthesis of Fault-Secure Microarchitectures. 429-433
  
• Manjote S. Haworth, William P. Birmingham:
  Towards Optimal System-Level Design. 434-438
  

Testing of Delay and Bridging Faults

• Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
  NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. 439-445
  
• William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Delay Fault Coverage and Performance Tradeoffs. 446-452
  
• Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
  Design for Testability for Path Delay faults in Sequential Circuits. 453-457
  
• Brian Chess, Tracy Larrabee:
  Bridge Fault simulation strategies for CMOS integrated Circuits. 458-462
  

Formal Verification

• June-Kyung Rho, Fabio Somenzi, Carl Pixley:
  Minimum Length Synchronizing Sequences of Finite State Machine. 463-468
  
• Jeffrey J. Joyce, Carl-Johan H. Seger:
  Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. 469-474
  
• Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan:
  A Unified Approach to Language Containment and Fair CTL Model Checking. 475-481
  

Panel

• William S. Johnson:
  Are EDA Platform Preferences About to Shift? (Panel Abstract). 482
  

Retiming and Timing Analysis in Sequential Synthesis

• Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
  Sequential Circuit Delay optimization Using Global Path Delays. 483-489
  
• Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Resynthesis of Multi-Phase Pipelines. 490-496
  
• Marios C. Papaefthymiou, Keith H. Randall:
  TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. 497-502
  

Fault Simulation and Diagnosis

• Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj:
  Diagnosis and Correction of Logic Design Errors in Digital Circuits. 503-508
  
• Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
  DRAFTS: Discretized Analog Circuit Fault Simulator. 509-514
  
• Wolfgang Meyer, Raul Camposano:
  Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. 515-519
  
• Sreejit Chakravarty, Yiming Gong:
  An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. 520-524
  

Placement and Floorplanning

• Tsu-chang Lee:
  A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules. 525-530
  
• Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
  Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach. 531-536
  
• Jun Dong Cho, Majid Sarrafzadeh:
  A Nuffer Distribution Algorithm for High-Speed Clock Routing. 537-543
  

Practical Design and Validation Techniques

• Masato Mogaki, Yoichi Shiraishi, Mitsuyuki Kimura, Tetsuro Hino:
  Cooperative Approach to a Practical Analog LSI Layout System. 544-549
  
• Gopi Ganapathy, Jacob A. Abraham:
  Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. 550-555
  
• Kenneth W. Wan, Roshan A. Gidwani:
  ABLE: AMD Backplane for Layout Engines. 556-560
  
• Steven G. Duvall:
  Practical Statistical Design of Complex Integrated Circuit Products. 561-565
  

Retiming and Scheduling

• Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha:
  Rotation Scheduling: A Loop Pipelining Algorithm. 566-572
  
• Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker:
  Critical Path Minimization Using Retiming and Algebraic Speed-Up. 573-577
  
• S. H. Huang, Y. L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang:
  A Tree-Based Scheduling Algorithm for Control-Dominated Circuits. 578-582
  
• Richard J. Cloutier, Donald E. Thomas:
  Synthesis of Pipelined Instruction Set Processors. 583-588
  

Panel

• Michael C. McFarland:
  Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract). 589
  

Performance-Driven Routing

• Kei-Yong Khoo, Jason Cong:
  An Efficient Multilayer MCM Router Based on Four-Via Routing. 590-595
  
• Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh:
  An Efficient Timing-Driven Global Routing Algorithm. 596-600
  
• Forbes D. Lewis, Wang Chia-Chi Pong:
  A Negative Reinforcement Method for PGA Routing. 601-605
  
• Jason Cong, Kwok-Shing Leung, Dian Zhou:
  Performance-Driven Interconnect Design Based on Distributed RC Delay Model. 606-611
  
• Masato Edahiro:
  A Clustering-Based Optimization Algorithm in Zero-Skew Routings. 612-616
  

Panel

• Ronald Collett:
  Multi-vendor Tool Integration Experiences (Panel Abstract). 617
  

Advances in Logic Synthesis

• Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Espresso-Signature: A New Exact Minimizer for Logic Functions. 618-624
  
• Olivier Coudert, Jean Christophe Madre, Henri Fraisse:
  A New Viewpoint on Two-Level Logic Minimization. 625-630
  
• Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli:
  Optimization of Combinational Logic Circuits Based on Compatible Gates. 631-636
  
• Hans Eveking, Stefan Höreth:
  Optimization and Resynthesis of Complex Data-Paths. 637-641
  
• Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula:
  BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. 642-647
  

Infrastructure from Process to Debugging

• Peter R. Sutton, Jay B. Brockman, Stephen W. Director:
  Design Management Using Dynamically Defined Flows. 648-653
  
• Mário J. Silva, Randy H. Katz:
  Active Documentation: A New Interface for VLSI Design. 654-660
  
• Ram Mandayam, Ranga Vemuri:
  Performance Specification Using Attributed Grammars. 661-667
  
• Cristian A. Giumale, Hilary J. Kahn:
  An Information Model of Time. 668-672
  
• Yehuda Kra:
  A Cross-Debugging Method for Hardware/Software Co-design Environments. 673-677
  

High Speed Interconnects Analysis

• Mattan Kamon, Michael J. Tsuk, Jacob White:
  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program. 678-683
  
• Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes:
  High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods. 684-690
  
• Mysore Sriram, Sung-Mo Kang:
  Fast Approximation of the Transient Response of Lossy Transmision Line Trees. 691-696
  
• Monjurul Haque, Salim Chowdhury:
  Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections. 697-701
  
• Hansruedi Heeb, Saila Ponnapalli, Albert E. Ruehli:
  Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits. 702-706
  

Russian CAE

• Valery Yarnikh:
  The State of CAD and VLSI in Russia. 707-708
  
• Yuri Tatarnikov:
  The State of VHDL in Russia. 709-711
  
• Alexander Birger:
  The State of Simulation in Russia. 712-715
  
• Valery M. Mikhov:
  The State of EDA in Russian Universities. 716-719
  

Electrical Modeling and Simulation

• Andrew T. Yang, Yu Liu, Jack T. Yao, R. R. Daniels:
  An Efficient Non-Quasi-Static Diode Model for Circuit Simulation. 720-725
  
• Haifang Liao, Wayne Wei-Ming Dai, Rui Wang, Fung-Yuel Chang:
  S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function. 726-731
  
• Eli Chiprout, Michel S. Nakhla:
  Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation. 732-736
  
• Chandramouli Visweswariah, Jalal A. Wehbeh:
  Incremental Event-Driven Simulation of Digital FET Circuits. 737-741
  

Panel

• John A. Darringer:
  Where in the World Should CAD Software be Made? (Panel Abstract). 742
  

Circuit Partitioning

• Charles J. Alpert, Andrew B. Kahng:
  Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. 743-748
  
• Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
  Spectral K-Way Ratio-Cut Partitioning and Clustering. 749-754
  
• Jason Cong, M'Lissa Smith:
  A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. 755-760
  
• Minshine Shih, Ernest S. Kuh:
  Quadratic Boolean Programming for Performance-Driven System Partitioning. 761-765
  

Panel

• Romesh Wadhwani:
  The Key to EDA Results: Component & Library Management (Panel Abstract). 766
  

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