33. DAC 1996: Las Vegas, Nevada, USA

Executive Forum, Panel: The EDA Year in Review: CEO's, The Press, and Users

High Speed Interconnect

• Mattan Kamon, Steve S. Majors:
  Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter. 2-7
  

Panel: PCB Synthesis - Is the Technology Ready for High Speed Design?

Power Analysis

• Janardhan H. Satyanarayana, Keshab K. Parhi:
  HEAT: Hierarchical Energy Analysis Tool. 9-14
  
• Andrew Wolfe:
  Opportunities and Obstacles in Low-Power System-Level CAD. 15-20
  
• Sasan Iman, Massoud Pedram:
  POSE: Power Optimization and Synthesis Environment. 21-26
  
• David Lidsky, Jan M. Rabaey:
  Early Power Exploration - A World Wide Web Application. 27-32
  

Current Directions in High Level Synthesis

• Raul Camposano:
  Behavioral Synthesis. 33-34
  
• Ehat Ercanli, Christos A. Papachristou:
  A Register File and Scheduling Model for Application Specific Processor Synthesis. 35-40
  
• Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar:
  Optimized Code Generation of Multiplication-free Linear Transforms. 41-46
  
• Chuck Monahan, Forrest Brewer:
  Concurrent Analysis Techniques for Data Path Timing Optimization. 47-50
  
• Jian Li, Rajesh K. Gupta:
  HDL Optimization Using Timed Decision Tables. 51-54
  

Analysis and Synthesis of Asynchronous Circuits

• Eric Verlind, Gjalt G. de Jong, Bill Lin:
  Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems. 55-58
  
• Alexei L. Semenov, Alexandre Yakovlev:
  Verification of asynchronous circuits using Time Petri Net unfolding. 59-62
  
• Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev:
  Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. 63-66
  
• Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson:
  A Technique for Synthesizing Distributed Burst-mode Circuits. 67-70
  
• Michael Theobald, Steven M. Nowick, Tao Wu:
  Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. 71-76
  
• Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick:
  Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. 77-82
  

New Frontiers in Partitioning

• Frank M. Johannes:
  Partitioning of VLSI Circuits and Systems. 83-87
  
• Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng:
  New Spectral Linear Placement and Clustering Approach. 88-93
  
• Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil:
  Characterization and Parameterized Random Generation of Digital Circuits. 94-99
  
• Shantanu Dutt, Wenyong Deng:
  A Probability-Based Approach to VLSI Circuit Partitioning. 100-105
  

Trends in Verification

• Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha:
  Verification of Electronic Systems. 106-111
  

Panel: Hot New Trends in Verification

Specialized Design Techniques for Speed and Power

• Anantha Chandrakasan, Isabel Yang, Carlin Vieri, Dimitri Antoniadis:
  Design Considerations and Tools for Low-voltage Digital System Design. 113-118
  
• Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser:
  VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems. 119-124
  
• Madhav P. Desai, Yao-Tsung Yen:
  A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. 125-130
  

Test and Fault Tolerance in High Level Synthesis

• Kenneth D. Wagner, Sujit Dey:
  High-Level Synthesis for Testability: A Survey and Perspective. 131-136
  
• Balakrishnan Iyer, Ramesh Karri:
  Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis. 137-142
  
• Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
  Lower Bounds on Test Resources for Scheduled Data Flow Graphs. 143-148
  

Issues in Discrete Simulation

• Antonio R. W. Todesco, Teresa H. Y. Meng:
  Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems. 149-154
  
• Peter Dahlgren:
  Oscillation Control in Logic Simulation using Dynamic Dominance Grahps. 155-160
  
• Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee:
  Compact Vector Generation for Accurate Power Simulation. 161-164
  
• Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram:
  Improving the Efficiency of Power Simulators by Input Vector Compaction. 165-168
  

Issues in Design Environments

• Idalina Videira, Paulo Veríssimo, Helena Sarmento:
  Efficient Communication in a Design Environment. 169-174
  
• Peter R. Sutton, Stephen W. Director:
  A Description Language for Design Process Management. 175-180
  
• John W. Hagerman, Stephen W. Director:
  Improved Tool and Data Selection in Task Management. 181-184
  
• Eric W. Johnson, Luis A. Castillo, Jay B. Brockman:
  Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process. 185-188
  

Panel: Gearing Up for the Technology Explosion

Tutorial: The SPICE FET Models: Pitfalls and Prospects

Combinational Logic Synthesis I

• Richard L. Rudell:
  Tutorial: Design of a Logic Synthesis System. 191-196
  
• Olivier Coudert:
  On Solving Covering Problems. 197-202
  

Pattern Generation for Test and Diagnosis

• Sungju Park:
  A New Complete Diagnosis Patterns for Wiring Interconnects. 203-208
  
• Chih-Ang Chen, Sandeep K. Gupta:
  A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. 209-214
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On Static Compaction of Test Sequences for Synchronous Sequential Circuits. 215-220
  

CAD for Analog and Mixed Signal ICs

• Bulent Basaran, Rob A. Rutenbar:
  An O(n) Algorithm for Transistor Stacking with Performance Constraints. 221-226
  
• Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli:
  Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design. 227-232
  
• Sanjay Sawant, Paul Giordano:
  RTL Emulation: The Next Leap in System Verification. 233-235
  
• Carsten Borchers, Lars Hedrich, Erich Barke:
  Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. 236-239
  

Panel: Core-Based Design for System-Level ASICs - Whose Job Is It?

Panel: A Common Standards Roadmap

Combinational Logic Synthesis II

• Chien-Chung Tsai, Malgorzata Marek-Sadowska:
  Multilevel Logic Synthesis for Arithmetic Functions. 242-247
  
• Jeffery P. Hansen, Masatoshi Sekine:
  Synthesis by Spectral Translation Using Boolean Decision Diagrams. 248-253
  
• Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy:
  Delay Minimal Decomposition of Multiplexers in Technology Mapping. 254-257
  
• Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
  Error Correction Based on Verification Techniques. 258-261
  

Design for Testability

• Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang:
  Layout Driven Selecting and Chaining of Partial Scan. 262-267
  
• Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee:
  Test Point Insertion: Scan Paths through Combinational Logic. 268-273
  
• Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng:
  Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. 274-279
  

Advances in Electrical Simulation

• Kevin J. Kerns, Andrew T. Yang:
  Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations. 280-285
  
• Jaijeet S. Roychowdhury, Robert C. Melville:
  Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits. 286-291
  
• Ricardo Telichevesky, Kenneth S. Kundert, Jacob White:
  Efficient AC and Noise Analysis of Two-Tone RF Circuits. 292-297
  

Mixed Signal Design

• L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen:
  Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. 298-303
  

Panel: Mixed Signal Designs: Are There Solutions Today?

Functional Verification of Microprocessors

• Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas:
  Code Generation and Analysis for the Functional Verification of Microprocessors. 305-310
  
• Val Popescu, Bill McNamara:
  Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor. 311-314
  
• Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang, Jim Nishimura:
  Hardware Emulation for Functional Verification of K5. 315-318
  
• James Monaco, David Holloway, Rajesh Raina:
  Functional Verification Methodology for the PowerPC 604 Microprocessor. 319-324
  
• Michael Kantrowitz, Lisa M. Noack:
  I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor. 325-330
  

High Level Power Optimization

• Anand Raghunathan, Sujit Dey, Niraj K. Jha:
  Glitch Analysis and Reduction in Register Transfer Level. 331-336
  
• Christos A. Papachristou, Mark Spining, Mehrdad Nourani:
  An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. 337-342
  
• Mani B. Srivastava, Miodrag Potkonjak:
  Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach. 343-348
  
• José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar:
  Scheduling Techniques to Enable Power Management. 349-352
  
• Aurobindo Dasgupta, Ramesh Karri:
  Electromigration Reliability Enhancement via Bus Activity Distribution. 353-356
  

3-D Parasitic Extraction

• Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi:
  A Sparse Image Method for BEM Capacitance Extraction. 357-362
  
• Narayan R. Aluru, V. B. Nadkarni, James White:
  A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis. 363-366
  
• Johannes Tausch, Jacob K. White:
  Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios. 367-370
  
• Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II:
  Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance. 371-376
  
• Joel R. Philips, Eli Chiprout, David D. Ling:
  Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms. 377-382
  

Routing Optimization for Performance

• Joe G. Xi, Wayne Wei-Ming Dai:
  Useful-Skew Clock Routing With Gate Sizing for Low Power Design. 383-388
  
• Madhav P. Desai, Radenko Cvijetic, James Jensen:
  Sizing of Clock Distribution Networks for High Performance CPU Chips. 389-394
  
• John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho:
  New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. 395-400
  
• Jaewon Oh, Iksoo Pyo, Massoud Pedram:
  Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming. 401-404
  
• Chung-Ping Chen, Yao-Wen Chang, D. F. Wong:
  Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. 405-408
  

Tutorial: How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together

• Robert C. Hutchins, Shankar Hemmady:
  How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together. 409-414
  

Functional Verification Techniques

• K. D. Jones, J. P. Privitera:
  The Automatic Generation of Functional Test Vectors for Rambus Designs. 415-420
  
• Françoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet:
  Functional Verification Methodology of Chameleon Processor. 421-426
  
• Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic:
  Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. 427-432
  

Power Estimation

• Alessandro Bogliolo, Luca Benini, Bruno Riccò:
  Power Estimation of Cell-Based CMOS Circuits. 433-438
  
• David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska:
  A New Hybrid Methodology for Power Estimation. 439-444
  
• Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma:
  A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits. 445-450
  

Optimization of Sequential Circuits

• Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Engineering Change in a Non-Deterministic FSM Setting. 451-456
  
• Mahesh A. Iyer, David E. Long, Miron Abramovici:
  Identifying Sequential Redundancies Without Search. 457-462
  
• Hiroyuki Higuchi, Yusuke Matsunaga:
  A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. 463-466
  
• Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
  Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. 467-470
  

Topics in Physical Design

• Andreas Koch:
  Module Compaction in FPGA-based Regular Datapaths. 471-476
  
• Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng:
  Network Partitioning into Tree Hierarchies. 477-482
  
• Danny Z. Chen, Xiaobo Hu:
  Efficient Approximation Algorithms for Floorplan Area Minimization. 483-486
  
• Chung-Ping Chen, Yao-Ping Chen, D. F. Wong:
  Optimal Wire-Sizing Formular Under the Elmore Delay Model. 487-490
  

Consumer Product Design

• Tetsuya Fujimoto, Takashi Kambe:
  VLSI Design and System Level Verification for the Mini-Disc. 491-496
  
• Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa:
  Design Methodologies for consumer-use video signal processing LSIs. 497-502
  
• Yasunori Miyahara, Yoshimoto Oumi, Seijiro Moriyama:
  Design Methodology for Analog High Frequency ICs. 503-508
  

Tutorial: Issues and Answers in CAD Tool Interoperability

• Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trivedi, Bill McCaffrey, Ted Vucurevich:
  Issues and Answers in CAD Tool Interoperability. 509-514
  

Hardware-Software Co-Design

• Jay K. Adams, Donald E. Thomas:
  The Design of Mixed Hardware/Software Systems. 515-520
  
• Steven Vercauteren, Bill Lin, Hugo De Man:
  Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. 521-526
  
• Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
  A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. 527-532
  

Timing and Power

• Andrew B. Kahng, Sudhakar Muddu:
  Analysis of RC Interconnections Under Ramp Input. 533-538
  
• Bernard N. Sheehan:
  An AWE Technique for Fast Printed Circuit Board Delays. 539-543
  
• Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi:
  RC-Interconnect Macromodels for Timing Simulation. 544-547
  
• Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang:
  iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. 548-551
  

Verification of Sequential Systems

• Jerry R. Burch:
  Techniques for Verifying Superscalar Microprocessors. 552-557
  
• Jeremy R. Levitt, Kunle Olukotun:
  A Scalable Formal Verification Methodology for Pipelined Microprocessors. 558-563
  
• C. Norris Ip, David L. Dill:
  State Reduction Using Reversible Rules. 564-567
  
• Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
  Formal Verification of Embedded Systems based on CFSM Networks. 568-571
  

Panel: Electronic Connectivity + EDA Data = Electronic Commerce

Experience with High Level Synthesis

• Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens:
  Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. 573-578
  
• J. Huisken, F. Welten:
  FADIC: Architectural Synthesis applied in IC Design. 579-584
  
• Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
  Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. 585-590
  

Analysis and Compilation for Embedded Software

• Guido Araujo, Sharad Malik, Mike Tien-Chien Lee:
  Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. 591-596
  
• Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
  Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures. 597-600
  
• Rajesh K. Gupta:
  Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems. 601-604
  
• Kei Suzuki, Alberto L. Sangiovanni-Vincentelli:
  Efficient Software Performance Estimation Methods for Hardware/Software Codesign. 605-610
  

Timing Modeling and Optimization

• Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi:
  An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. 611-616
  
• V. Chandramouli, Karem A. Sakallah:
  Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. 617-622
  
• José Luis Neves, Eby G. Friedman:
  Optimal Clock Skew Scheduling Tolerant to Process Variations. 623-628
  

Decision Diagrams and Their Application

• Yusuke Matsunaga:
  An Efficient Equivalence Checker for Combinational Circuits. 629-634
  
• Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  High Performance BDD Package By Exploiting Memory Hiercharchy. 635-640
  
• Tony Stornetta, Forrest Brewer:
  Implementation of an Efficient Parallel BDD Package. 641-644
  
• Edmund M. Clarke, Manpreet Khaira, Xudong Zhao:
  Word Level Model Checking - Avoiding the Pentium FDIV Error. 645-648
  

Formal Methods

• Manish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant:
  Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. 649-654
  
• Ilan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver:
  RuleBase: An Industry-Oriented Formal Verification Tool. 655-660
  
• Randal E. Bryant:
  Bit-Level Analysis of an SRT Divider Circuit. 661-665
  
• Ásgeir Th. Eiríksson:
  Integrating Formal Verification Methods with A Conventional Project Design Flow. 666-671
  

Applications for Hardware/Software Codesign

• Bill Lin:
  A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications. 672-677
  
• Steven Vercauteren, Bill Lin, Hugo De Man:
  A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures. 678-683
  
• Benny Schnaider, Einat Yogev:
  Software Development in a Hardware Simulation Environment. 684-689
  
• Vojin Zivojnovic, Heinrich Meyr:
  Compiled HW/SW Co-Simulation. 690-695
  

Power Estimation and Retiming

• Diana Marculescu, Radu Marculescu, Massoud Pedram:
  Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation. 696-701
  
• Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
  Energy Characterization based on Clustering. 702-707
  
• Soha Hassoun, Carl Ebeling:
  Architectural Retiming: Pipelining Latency-Constrained Circuts. 708-713
  
• Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak:
  Optimizing Systems for Effective Block-Processing: The k-Delay Problem. 714-719
  

Technology Dependent Performance Driven Synthesis

• Peichen Pan, C. L. Liu:
  Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. 720-725
  
• Jason Cong, Yean-Yow Hwang:
  Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. 726-729
  
• Christian Legl, Bernd Wurth, Klaus Eckl:
  A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs. 730-733
  
• Olivier Coudert, Ramsey W. Haddad, Srilatha Manne:
  New Algorithms for Gate Sizing: A Comparative Study. 734-739
  
• Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda:
  Post-Layout Optimization for Deep Submicron Design. 740-745
  

Layout Analysis and Optimization

• Cyrus Bamji, Enrico Malavasi:
  Enhanced Network Flow Algorithm for Yield Optimization. 746-751
  
• Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang:
  Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. 752-757
  
• Arjan J. van Genderen, N. P. van der Meijs:
  Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. 758-763
  
• P. J. H. Elias, N. P. van der Meijs:
  Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. 764-769
  

Panel: System Synthesis: Can we Meet the Challenges to Come?

Hardware Description Language Techniques

• Douglas J. Smith:
  VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. 771-776
  
• Hans Sahm, Claus Mayer, Jörg Pleickhardt, Johannes Schuck, Stefan Späth:
  VDHL Development System and Coding Standard. 777-782
  

Power Minimization in IC Design

• De-Sheng Chen, Majid Sarrafzadeh:
  An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing. 783-788
  
• Bernhard Rohfleisch, Alfred Kölbl, Bernd Wurth:
  Reducing Power Dissipation after Technology Mapping by Structural Transformations. 789-794
  
• Xiangfeng Chen, Peichen Pan, C. L. Liu:
  Desensitization for Power Reduction in Sequential Circuits. 795-800
  

Advanced Test Solutions

• Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape:
  Serial Fault Emulation. 801-806
  
• Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
  Partial Scan Design Based on Circuit State Information. 807-812
  
• Laurence Goodby, Alex Orailoglu:
  Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. 813-818
  

Technology Optimization for Cells and Systems

• Aurobindo Dasgupta, Ramesh Karri:
  Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing. 819-824
  
• Arun N. Lokanathan, Jay B. Brockman, John E. Renaud:
  A Methodology for Concurrent Fabrication Process/Cell Library Optimization. 825-830
  
• Mien Li, Linda S. Milor:
  Computing Parametric Yield Adaptively Using Local Linear Models. 831-836
  

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