36. DAC 1999: New Orleans, LA, USA

• Jing-Rebecca Li, Frank Wang, Jacob White:
  An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect. 1-6
  
• Chung-Ping Chen, D. F. Wong:
  Error Bounded Padé Approximation via Bilinear Conformal Transformation. 7-12
  
• Pavan K. Gunupudi, Michel S. Nakhla:
  Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques. 13-16
  
• Bernard N. Sheehan:
  ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization. 17-21
  
• Mukul R. Prasad, Philip Chong, Kurt Keutzer:
  Why is ATPG Easy? 22-28
  
• Rolf Drechsler, Wolfgang Günther:
  Using Lower Bounds During Dynamic BDD Minimization. 29-32
  
• Gang Qu, Jennifer L. Wong, Miodrag Potkonjak:
  Optimization-Intensive Watermarking Techniques for Decision Problems. 33-36
  
• Ali Dasdan, Sandy Irani, Rajesh K. Gupta:
  Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems. 37-42
  
• Daniel Gajski:
  IP-based Design Methodology. 43
  
• Pai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partridge, Gaetano Borriello:
  ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems. 44-49
  
• Marcello Dalpasso, Alessandro Bogliolo, Luca Benini:
  Virtual Simulation of Distributed IP-based Designs. 50-55
  
• Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
  Common-Case Computation: A High-Level Technique for Power and Performance Optimization. 56-61
  
• Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang:
  Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. 62-67
  
• Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
  Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. 68-71
  
• Vijay Sundararajan, Keshab K. Parhi:
  Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. 72-75
  
• Raul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto L. Sangiovanni-Vincentelli, Jim Lansford:
  HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night. 76-77
  
• Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan:
  Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. 78-83
  
• Jiang Hu, Sachin S. Sapatnekar:
  FAR-DS: Full-Plane AWE Routing with Driver Sizing. 84-89
  
• Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang:
  Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. 90-95
  
• Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz:
  Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. 96-99
  
• Prashant Saxena, C. L. Liu:
  Crosstalk Minimization Using Wire Perturbations. 100-103
  
• Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
  Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. 104-109
  
• Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
  Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. 110-115
  
• Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken:
  CAD Directions for High Performance Asynchronous Circuits. 116-121
  
• Jörg Henkel:
  A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems. 122-127
  
• Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
  Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. 128-133
  
• Youngsoo Shin, Kiyoung Choi:
  Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. 134-139
  
• Wen-Tsong Shiue, Chaitali Chakrabarti:
  Memory Exploration for Low Power, Embedded Systems. 140-145
  
• Ravi Sharma:
  Distributed Application Development with Inferno. 146-150
  
• David Stepner, Nagarajan Rajan, David Hui:
  Embedded Application Design Using a Real-Time OS. 151-156
  
• Ken Arnold:
  The Jini Architecture: Dynamic Services in a Flexible Network. 157-162
  
• Dennis Abts, Mike Roberts:
  Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment. 163-168
  
• Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu:
  Functional Verification of the Equator MAP1000 Microprocessor. 169-174
  
• Shmuel Ur, Yaov Yadin:
  Micro Architecture Coverage Directed Generation of Test Programs. 175-180
  
• You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung:
  Verification of a Microprocessor Using Real World Applications. 181-184
  
• David Van Campenhout, Trevor N. Mudge, John P. Hayes:
  High-Level Test Generation for Design Verification of Pipelined Microprocessors. 185-188
  
• Laurent Fournier, Anatoly Koyfman, Moshe Levinger:
  Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture. 189-194
  
• Roland W. Freund:
  Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace Algorithms. 195-200
  
• Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas:
  Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. 201-206
  
• Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira:
  Robust Rational Function Approximation Algorithm for Model Generation. 207-212
  
• Reinaldo A. Bergamaschi:
  Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis. 213-218
  
• Jianwen Zhu, Daniel Gajski:
  Soft Scheduling in High Level Synthesis. 219-224
  
• Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko:
  Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. 225-230
  
• Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
  Maximizing Performance by Retiming and Clock Skew Scheduling. 231-236
  
• Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl:
  A Practical Approach to Multiple-Class Retiming. 237-242
  
• Peichen Pan:
  Performance-Driven Integration of Retiming and Resynthesis. 243-246
  
• Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
  Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. 247-252
  
• Joseph A. Fisher:
  Customized Instruction-Sets for Embedded Processors. 253-257
  
• Samuel P. Harbison:
  System-Level Hardware/Software Trade-offs. 258-259
  
• Jonah McLeod, Nozar Azarakhsh, Glen Ewing, Paul Gingras, Scott Reedstrom, Chris Rowen:
  Functional Verification - Real Users, Real Problems, Real Opportunities (Panel). 260-261
  
• Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
  A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. 262-267
  
• Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura:
  An O-Tree Representation of Non-Slicing Floorplan and Its Applications. 268-273
  
• Florin Balasa, Koen Lampaert:
  Module Placement for Analog Layout Using the Sequence-Pair Representation. 274-279
  
• Martin Grajcar:
  Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor System. 280-285
  
• Sanghun Park, Kiyoung Choi:
  Performance-Driven Scheduling with Bit-Level Chaining. 286-291
  
• Steve Haynal, Forrest Brewer:
  A Model for Scheduling Protocol-Constrained Components and Environments. 292-295
  
• Luiz C. V. dos Santos, Jochen A. G. Jess:
  A Reordering Technique for Efficient Code Motion. 296-299
  
• Yatin Vasant Hoskote, Timothy Kam, Pei-Hsin Ho, Xudong Zhao:
  Coverage Estimation for Symbolic Model Checking. 300-305
  
• Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
  Improving Symbolic Traversals by Means of Activity Profiles. 306-311
  
• Shankar G. Govindaraju, David L. Dill, Jules P. Bergmann:
  Improved Approximate Reachability Using Auxiliary State Variables. 312-316
  
• Armin Biere, Alessandro Cimatti, Edmund M. Clarke, Masahiro Fujita, Yunshan Zhu:
  Symbolic Model Checking Using SAT Procedures instead of BDDs. 317-320
  
• Johnson Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak:
  Power Efficient Mediaprocessors: Design Space Exploration. 321-326
  
• Arnout Vandecappelle, Miguel Miranda, Erik Brockmeyer, Francky Catthoor, Diederik Verkest:
  Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback. 327-332
  
• Lode Nachtergaele, Bart Vanhoof, Mercedes Peón, Gauthier Lafruit, Jan Bormans, Ivo Bolsens:
  Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System. 333-336
  
• Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels:
  A 10 Mbit/s Upstream Cable Modem with Automatic equalization. 337-340
  
• Kurt Keutzer, Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns:
  Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic. 341-342
  
• George Karypis, Vipin Kumar:
  Multilevel k-way Hypergraph Partitioning. 343-348
  
• Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
  Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. 349-354
  
• Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
  Hypergraph Partitioning with Fixed Vertices. 355-359
  
• Sung-Woo Hur, John Lillis:
  Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. 360-366
  
• Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee:
  An Approxmimate Algorithm for Delay-Constraint Technology Mapping. 367-372
  
• Jason Cong, Yean-Yow Hwang, Songjie Xu:
  Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. 373-378
  
• Priyadarshan Patra, Unni Narayanan:
  Automated Phase Assignment for the Synthesis of Low Power Domino Circuits. 379-384
  
• Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann:
  Enhancing Simulation with BDDs and ATPG. 385-390
  
• Valeria Bertacco, Maurizio Damiani, Stefano Quer:
  Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. 391-396
  
• Miroslav N. Velev, Randal E. Bryant:
  Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors. 397-401
  
• Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger:
  Parametric Representations of Boolean Constraints. 402-407
  
• Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass:
  Vertical Benchmarks for CAD. 408-413
  
• Xiaobo Hu, Garrison W. Greenwood, S. Ravichandran, Gang Quan:
  A Framework for User Assisted Design Space Exploration. 414-419
  
• Benoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, François Pogodalla:
  Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design. 420-424
  
• Johann Notbauer, Thomas W. Albrecht, Georg Niedrist, Stefan Rohringer:
  Verification and Management of a Multimillion-Gate Embedded Core Design. 425-428
  
• Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker:
  Parasitic Extraction Accuracy - How Much is Enough? 429
  
• Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De:
  Mixed-V_th (MVT) CMOS Circuit Design Methodology for Low Power Applications. 430-435
  
• Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw:
  Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. 436-441
  
• Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
  Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. 442-445
  
• Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
  A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. 446-451
  
• Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan:
  Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. 452-459
  
• Jason Cong, Honching Li, Chang Wu:
  Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. 460-465
  
• Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long:
  Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. 466-471
  
• Amir H. Salek, Jinan Lou, Massoud Pedram:
  MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search. 472-478
  
• Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
  Buffer Insertion with Accurate Gate and Interconnect Delay Computation. 479-484
  
• Joon-Seo Yim, Chong-Min Kyung:
  Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design. 485-490
  
• Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli:
  A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. 491-496
  
• Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro:
  Improved Selay Prediction for On-Chip Buses. 497-501
  
• Chung-Ping Chen, Noel Menezes:
  Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. 502-506
  
• Jason Cong, David Zhigang Pan:
  Interconnect Estimation and Dlanning for Deep Submicron Designs. 507-510
  
• Luciano Lavagno, Ellen Sentovich:
  ECL: A Specification Environment for System-Level Design. 511-516
  
• Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich:
  Representation of Function Variants for Embedded System Optimization and Synthesis. 517-522
  
• Jules P. Bergmann, Mark Horowitz:
  Vex - A CAD Toolbox. 523-528
  
• Juan Antonio Carballo, Stephen W. Director:
  Constraint Management for Collaborative Electronic Design. 529-534
  
• Kristofer S. J. Pister, Albert P. Pisano, Nicholas Swart, Mike Horton, John Rychcik, John R. Gilbert, Gerry K. Fedder:
  MEMS CAD Beyond Multi-Million Transistors (Panel). 535-536
  
• Johannes Tausch, Jacob K. White:
  A Multiscale Method for Fast Capacitance Extraction. 537-542
  
• Vikram Jandhyala, Scott Savage, J. Eric Bracken, Zoltan J. Cendes:
  Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes. 543-548
  
• Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang:
  Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. 549-554
  
• Qinru Qiu, Massoud Pedram:
  Dynamic Power Management Based on Continuous-Time Markov Decision Processes. 555-561
  
• Mauro Chinosi, Roberto Zafalon, Carlo Guardiani:
  Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning. 562-567
  
• Milos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak:
  Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. 568-573
  
• Daniel Geist, Giora Biran, Tamarah Arons, Michael Slavkin, Yvgeny Nustov, Monica Farkas, Karen Holtz, Andy Long, Dave King, Steve Barret:
  A Methodology for the Verification of a ``System on Chip''. 574-579
  
• Ing-Jer Huang, Tai-An Lu:
  ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers. 580-585
  
• Christos A. Papachristou, F. Martin, Mehrdad Nourani:
  Microprocessor Based Testing for Core-Based System on Chip. 586-591
  
• Hema Kapadia, Mark Horowitz:
  Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology. 592-597
  
• Imed Moussa, Zoltan Sugar, Rodolph Suescun, Mario Diaz-Nava, Marco Pavesi, Salvatore Crudo, Luca Gazi, Ahmed Amine Jerraya:
  Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper. 598-603
  
• Darko Kirovski, Miodrag Potkonjak:
  Engineering Change: Methodology and Applications to Behavioral and System Synthesis. 604-609
  
• André DeHon, John Wawrzynek:
  Reconfigurable Computing: What, Why, and Implications for Design Automation. 610-615
  
• Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss:
  An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. 616-622
  
• Alexandro M. S. Adário, Eduardo L. Roehe, Sergio Bampi:
  Dynamically Reconfigurable Architecture for Image Processor Applications. 623-628
  
• Onuttom Narayan, Jaijeet S. Roychowdhury:
  Multi-Time Simulation of Voltage-Controlled Oscillators. 629-634
  
• Dan Feng, Joel R. Phillips, Keith Nabors, Kenneth S. Kundert, Jacob White:
  Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach. 635-640
  
• Ognen J. Nastov, Jacob White:
  Time-Mapped Harmonic Balance. 641-646
  
• Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham:
  Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. 647-652
  
• Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
  Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. 653-659
  
• Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni:
  Multiple Error Diagnosis Based on Xlists. 660-665
  
• Farzan Fallah, Pranav Ashar, Srinivas Devadas:
  Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. 666-671
  
• Lionel Bening:
  A Two-State Methodology for RTL Logic Simulation. 672-677
  
• Cordula Hansen, Francisco Nascimento, Wolfgang Rosenstiel:
  An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. 678-683
  
• Miron Abramovici, José T. de Sousa, Daniel G. Saab:
  A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. 684-690
  
• Fatih Kocan, Daniel G. Saab:
  Dynamic Fault Diagnosis on Reconfigurable Hardware. 691-696
  
• Xiaohan Zhu, Bill Lin:
  Hardware Compilation for FPGA-Based Configurable Computing Machines. 697-702
  
• D. J. Eaglesham:
  0.18m CMOS and Beyond. 703-708
  
• Ching-Te Chuang, Ruchir Puri:
  SOI Digital CMOS VLSI - a Design Perspective. 709-714
  
• Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
  Equivalent Elmore Delay for RLC Trees. 715-720
  
• Yehea I. Ismail, Eby G. Friedman:
  Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. 721-724
  
• Abdallah Tabbara, Robert K. Brayton, A. Richard Newton:
  Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. 725-730
  
• Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah:
  Functional Timing Analysis for IP Characterization. 731-736
  
• Richard Raimi, Jacob A. Abraham:
  Detecting False Timing Paths: Experiments on PowerPC Microprocessors. 737-741
  
• Han Bin Kim, Dong Sam Ha, Takeshi Takahashi:
  On ILP Formulations for Built-In Self-Testable Data Path Synthesis. 742-747
  
• Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik:
  Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. 748-753
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. 754-759
  
• Yi-Min Jiang, Kwang-Ting Cheng:
  Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. 760-765
  
• Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung:
  A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. 766-771
  
• Ramesh Harjani, Bapiraju Vinnakota:
  Digital Aetection of Analog Parametric Faults in SC Filters. 772-777
  
• Dyson Wilkes, M. M. Kamal Hashmi:
  Application of High Level Interface-Based Design to Telecommunications System Hardware. 778-783
  
• Patrick Schaumont, Radim Cmar, Serge Vernalde, Marc Engels, Ivo Bolsens:
  Hardware Reuse at the Behavioral Level. 784-789
  
• Tommy Kuhn, Wolfgang Rosenstiel, Udo Kebschull:
  Description and Simulation of Hardware/Software Systems with Java. 790-793
  
• Josef Fleischmann, Klaus Buchenrieder, Rainer Kress:
  Java Driven Codesign and Prototyping of Networked Embedded Systems. 794-797
  
• Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser:
  Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). 798
  
• Andrew B. Kahng, Y. C. Pati:
  Subwavelength Lithography and Its Potential Impact on Design and EDA. 799-804
  
• Marco Sgroi, Luciano Lavagno:
  Synthesis of Embedded Software Using Free-Choice Petri Nets. 805-810
  
• Ying Zhao, Sharad Malik:
  Exact Memory Size Estimation for Array Computations without Loop Unrolling. 811-816
  
• Steven Bashford, Rainer Leupers:
  Constraint Driven Code Selection for Fixed-Point DSPs. 817-822
  
• Alain Pegatoquet, Emmanuel Gresset, Michel Auguin, Luc Bianco:
  Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations. 823-826
  
• Asawaree Kalavade, Joe Othmer, Bryan D. Ackland, Kanwar Jit Singh:
  Software Environment for a Multiprocessor DSP. 827-830
  
• John Lach, William H. Mangione-Smith, Miodrag Potkonjak:
  Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks. 831-836
  
• Arlindo L. Oliveira:
  Robust Techniques for Watermarking Sequential Circuit Designs. 837-842
  
• Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
  Effective Iterative Techniques for Fingerprinting Design IP. 843-848
  
• Inki Hong, Miodrag Potkonjak:
  Behavioral Synthesis Techniques for Intellectual Property Protection. 849-854
  
• James Goodman, Anantha Chandrakasan, Abram P. Dancy:
  Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter. 855-860
  
• Massoud Pedram, Qing Wu:
  Design Considerations for Battery-Powered Electronics. 861-866
  
• Tajana Simunic, Luca Benini, Giovanni De Micheli:
  Cycle-Accurate Simulation of Energy Consumption in Embedded Systems. 867-872
  
• Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist:
  Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. 873-878
  
• Timothy P. Kurzweg, Steven P. Levitan, Philippe J. Marchand, Jose A. Martinez, Kurt R. Prough, Donald M. Chiarulli:
  A CAD Tool for Optical MEMS. 879-884
  
• Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu:
  On Thermal Effects in Deep Sub-Micron VLSI Interconnects. 885-891
  
• D. Allen, D. Behrends, B. Stanisic:
  Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology. 892-897
  
• Gangadhar Konduri, Anantha Chandrakasan:
  A Framework for Collaborative and Distributed Web-Based Design. 898-903
  
• Phillip Restle, Albert E. Ruehli, Steven G. Walker:
  Dealing with Inductance in High-Speed Chip Design. 904-909
  
• Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White:
  Interconnect Analysis: From 3-D Structures to Circuit Models. 910-914
  
• Michael W. Beattie, Lawrence T. Pileggi:
  IC Analyses Including Extracted Inductance Models. 915-920
  
• Shannon V. Morton:
  On-Chip Inductance Issues in Multiconductor Systems. 921-926
  
• George Hadjiyiannis, Pietro Russo, Srinivas Devadas:
  A Methodology for Accurate Performance Evaluation in Architecture Exploration. 927-932
  
• Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr:
  LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. 933-938
  
• Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung:
  Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. 939-944
  
• Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley:
  MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. 945-950
  
• Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri:
  Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. 951-957
  
• Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
  Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. 958-963
  
• Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic:
  Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. 964-969
  
• Mike Benjamin, Daniel Geist, Alan Hartman, Gérard Mas, Ralph Smeets, Yaron Wolfsthal:
  A Study in Coverage-Driven Test Generation. 970-975
  
• Wanli Jiang, Bapiraju Vinnakota:
  IC Test Using the Energy Consumption Ratio. 976-981
  
• C. Patrick Yue, S. Simon Wong:
  Design Strategy of On-Chip Inductors for Highly Integrated RF Systems. 982-987
  
• N. R. Belk, M. R. Frei, M. Tsai, A. J. Becker, K. L. Tokuda:
  The Simulation and Design of Integrated Inductors. 988-993
  
• Maria del Mar Hershenson, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee:
  Optimization of Inductor Circuits via Geometric Programming. 994-998
  
• Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani:
  Panel: What is the Proper System on Chip Design Methodology. 999
  

Last update Sun May 26 01:44:50 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page