DATE 2002: Paris, France

Plenary - Keynote Session

How to Choose Semiconductor IP?

Formal Verification of Complex Designs

Cooling Layout Arrangements

Defect Oriented Test

Power Analysis and Management in Networks and Processors

Panel - What is the Right IP Business Model?

SAT and BDD Techniques

Technology and Interconnect Issues in Low Power Design

Advanced Mixed Signal Test

Collaborative Design

Panel - Who Owns the Platform?

Embedded Tutorial - The Need for Infrastructure IP in SoCs

Advances in Logic Synthesis

Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design

EDA Tools for RF: Myth or Reality?

Platform-Based Design and Virtual-Component Reuse

Analogue Circuit Characterisation and Simulation

Panel - MEDEA+ and ITRS Roadmaps

Asynchronous Circuits and Clock Scheduling

Analogue and Mixed-Signal Systems

BIST Diagnosis and DFT

Code and Memory Optimization in Co-Design

Network on a Chip

Low Power Architectures and Software

Nitty Gritty Details of Layout Design

SoC and System Test

Modelling and Synthesis of Embedded Systems

Panel - Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs

Reconfigurable Architectures

Analogue Modelling, Layout and Sizing

Test Resource Partitioning for Embedded Cores

System Level Simulation and Modelling

Deep Submicron Design and Timing Closure

Reconfigurable SoC - What Will it Look Like?

Layout Aware Logic Synthesis

Buffering and Tapering

Automatic Design Debug and TPG

Object Oriented System Specification and Design

UML: Using the Unified Modeling Language for Embedded System Specification

Real-Time Embedded Systems

Interconnect Modelling

On-Line Testing and Fault Tolerance

Design Space Evaluation

From System Specification to Layout: Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications

Architectural Level Synthesis

Advanced Linear Modelling Techniques

Memory Testing and ATPG Issues

Embedded Software Performance Analysis and Optimization

Technical Plenary - 40 Years of EDA

Design Technology for Networked Reconfigurable FPGA Platforms

High-Level Synthesis and Asynchronous Pipelines

Coupling and Switching Noise Modelling within Integrated Circuits

Formal Verification Techniques: Industrial Status and Perspectives

Power Optimization for Embedded Processor

Poster Sessions