DATE 2003:
Munich,
Germany
2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany.
IEEE Computer Society 2003, ISBN 0-7695-1870-2 
@proceedings{DBLP:conf/date/2003,
title = {2003 Design, Automation and Test in Europe Conference and Exposition
(DATE 2003), 3-7 March 2003, Munich, Germany},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-1870-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Volume I
Plenary:
Keynote Session
Topic:
Ambient Intelligence Visions and Achievements:
Linking Abstract Ideas to Real-World Concepts
Energy-Efficient Memory Systems
- Alberto Macii, Enrico Macii, Massimo Poncino:
Improving the Efficiency of Memory Partitioning by Address Clustering.
10018-10023
- Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon:
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.
10024-10029
- Peter Petrov, Alex Orailoglu:
Power Efficiency through Application-Specific Instruction Memory Transformations.
10030-10035
- Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida:
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.
10036-10043
Embedded Tutorial:
Circuit,
Platform Design and Test Challenges in Technologies Beyond 90nm
Uncertainty
Hot Topic:
Scaling into Ambient Intelligence
Power-Aware Design and Synthesis
- Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang:
Masking the Energy Behavior of DES Encryption.
10084-10089
- Dong Wu, Bashir M. Al-Hashimi, Petru Eles:
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
10090-10095
- Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy:
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
10096-10103
Test Data Compression
- Wenjing Rao, Alex Orailoglu:
Virtual Compression through Test Vector Stitching for Scan Based Designs.
10104-10109
- Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch:
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.
10110-10115
- Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre:
A Technique for High Ratio LZW Compression.
10116-10121
- Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski:
Fast Computation of Data Correlation Using BDDs.
10122-10129
Operating System Abstraction and Targeting (Embedded Software Forum)
Analysis of Jitter and Noise for Analogue Systems and SD Modelling and Simulation
- Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi:
Noise Macromodel for Radio Frequency Integrated Circuits.
10150-10155
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney:
Approximation Approach for Timing Jitter Characterization in Circuit Simulators.
10156-10161
- Ewout Martens, Georges G. E. Gielen:
A Model of Computation for Continuous-Time ?-? Modulators.
10162-10167
- R. Castro-López, Francisco V. Fernández, F. Medeiro, Ángel Rodríguez-Vázquez:
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.
10168-10175
Hot Topic:
Securing Your Mobile Appliance:
New Challenges for the System Designer
Scheduling and Analysis of Embedded Systems
Recent Advances in DFT and BIST
Analogue and RF Modelling,
Simulation and Optimisation
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors.
10238-10243
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney:
A New Simulation Technique for Periodic Small-Signal Analysis.
10244-10249
- Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Generalized Posynomial Performance Modeling.
10250-10255
- Bart De Smedt, Georges G. E. Gielen:
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits.
10256-10263
Architectural Level Synthesis
- María C. Molina, José M. Mendías, Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage.
10264-10269
- Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs.
10270-10275
- Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya:
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.
10276-10281
- Kyeong Keol Ryu, Vincent John Mooney:
Automated Bus Generation for Multiprocessor SoC Design.
10282-10289
Scheduling in Reconfigurable Computing
Delay Testing and Diagnosis
Embedded Tutorial:
Embedded Operating Systems for SoC (Embedded Software Forum)
Networks-on-Chip
- Terry Tao Ye, Luca Benini, Giovanni De Micheli:
Packetized On-Chip Interconnect Communication Analysis for MPSoC.
10344-10349
- Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
10350-10355
- Frank Gilbert, Michael J. Thul, Norbert Wehn:
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .
10356-10363
System Level Modelling
Hot Topic:
Runtime Reconfigurable Systems on Chip - An Industry Perspective
Hot Topic:
Creating Value Through Test
Software Optimisation for Embedded Systems (Embedded Software Forum
Global Approaches to Layout Synthesis
Platform Design and IP Reuse Methods
Panel:
Reconfigurable Computing - Different Perspectives
Analogue and Defect-Oriented Testing
- Doris Lupea, Udo Pursche, Hans-Joachim Jentschel:
RF-BIST: Loopback Spectral Signature Analysis.
10478-10483
- Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter:
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation.
10484-10489
- Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti:
On Modeling Cross-Talk Faults.
10490-10495
- Martin John Burbidge, Jim Tijou, Andrew Richardson:
Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops.
10496-10503
Energy Aware Software Techniques (Embedded Software Forum)
- Venkata Syam P. Rapaka, Diana Marculescu:
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications.
10504-10509
- Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy:
Runtime Code Parallelization for On-Chip Multiprocessors.
10510-10515
- Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal:
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
10516-10523
Interconnect Modelling and Signal Integrity
System Level Simulation
Design Space Exploration for Reconfigurable Computing
On-Line Testing and Self-Repair
Hot Topic:
Safe Automotive Software Development (Embedded Software Forum)
Mixed-Signal Design Techniques
- Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits.
10624-10629
- Carsten Wegener, Michael Peter Kennedy:
Linear Model-Based Error Identification and Calibration for Data Converters.
10630-10635
- Miquel Albiol, José Luis González, Eduard Alarcón:
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters.
10636-10641
- Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
10642-10649
Design Space Exploration
- Arijit Ghosh, Tony Givargis:
Analytical Design Space Exploration of Caches for Embedded Systems.
10650-10655
- Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere:
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs.
10656-10661
- Laura Vanzago, Bishnupriya Bhattacharya, Joel Cambonie, Luciano Lavagno:
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform.
10662-10667
- William Fornaciari, P. Micheli, Fabio Salice, L. Zampella:
A First Step Towards Hw/Sw Partitioning of UML Specifications.
10668-10673
- Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe Diguet, Mohamed Abid, Jean Luc Philippe:
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs.
10674-10681
Low Power Architectures
- Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy Estimation for Extensible Processors.
10682-10687
- Jingcao Hu, Radu Marculescu:
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures.
10688-10693
- Wei-Chung Cheng, Massoud Pedram:
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface.
10694-10699
- Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.
10700-10705
- Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
10706-10713
System-on-Chip Testing
- Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Low-Cost Software-Based Self-Testing of RISC Processor Cores.
10714-10719
- Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
10720-10725
- Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Test Data Compression: The System Integrator's Perspective.
10726-10731
- Zahra Sadat Ebadi, André Ivanov:
Time Domain Multiplexed TAM: Implementation and Comparison.
10732-10737
- Sandeep Kumar Goel, Erik Jan Marinissen:
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.
10738-10741
- Qiang Xu, Nicola Nicolici:
Delay Fault Testing of Core-Based Systems-on-a-Chi.
10744-10752
Synthesis and Analysis of Digital Circuits
Embedded System Architectures (Embedded Software Forum)
- Amit Agarwal, Kaushik Roy, T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology.
10778-10783
- G. Surendra, Subhasis Banerjee, S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.
10784-10789
- Tudor Dumitras, Radu Marculescu:
On-Chip Stochastic Communication.
10790-10795
- Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhary, Ismail Kadayif:
An Integrated Approach for Improving Cache Behavior.
10796-10801
- Newton Cheung, Jörg Henkel, Sri Parameswaran:
Rapid Configuration and Instruction Selection for an ASIP: A Case Study.
10802-10809
Specification and Verification in Action
- Yakov Novikov:
Local Search for Boolean Relations on the Basis of Unit Propagation.
10810-10815
- Amit Goel, Randal E. Bryant:
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis.
10816-10821
- Shuo Sheng, Michael S. Hsiao:
Efficient Preimage Computation Using A Novel Success-Driven ATPG.
10822-10827
- Abhik Roychoudhury, Tulika Mitra, S. R. Karri:
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.
10828-10833
- Avi Ziv:
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions .
10834-10841
Hot Topic:
RF Design Technology for Highly Integrated Communication Systems
Zoning Chip Estate
Panel:
Transaction Based Design:
Another Buzzword or the Solution to a Design Problem?
Trust in SAT-Based Verification?
Transformations for Real-Time Software (Embedded Software Forum)
Synthesis Tools for Asynchronous Circuits
Collaborative Design and WWW-Based Tools
Performance Optimisation in Hardware/Software Codesign
- Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas:
Layered, Multi-Threaded, High-Level Performance Design.
10954-10959
- Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles:
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities.
10960-10965
- Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
10966-10973
Dynamic Resource Management for Reconfigurable Systems
Advances in Test Pattern Generation
Analogue and Digital Simulation
Low Power Software (Embedded Software Forum)
Application Specific Memory Synthesis
CAD for Analogue Design,
Design Methodologies and Physical Design
- Martin Vogels, Georges G. E. Gielen:
Figure of Merit Based Selection of A/D Converters.
11090-11091
- Oliver Kraus, Martin Padeffke:
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines.
11092-11093
- Johnson S. Kin, José Luis Pino:
Multithreaded Synchronous Data Flow Simulation.
11094-11095
- Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese:
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.
11096-11097
- Simona Doboli, Gaurav Gothoskar, Alex Doboli:
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering.
11098-11099
- Abhijit K. Deb, Johnny Öberg, Axel Jantsch:
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology.
11100-11101
- Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.
11102-11103
- Wonjoon Choi, Kia Bazargan:
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration.
11104-11105
- Alessandro Girardi, Sergio Bampi:
LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.
11106-11107
- Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram:
Symbolic Analysis of Nonlinear Analog Circuits.
11108-11109
- Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich:
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects.
11110-11111
- Seung Hoon Choi, Kaushik Roy:
A New Crosstalk Noise Model for DOMINO Logic Circuits.
11112-11113
- Li Ding, Pinaki Mazumder:
Modeling Noise Transfer Characteristic of Dynamic Logic Gates.
11114-11117
Reconfigurable Computing and Systems Design
- Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit:
Heterogeneous Programmable Logic Block Architectures.
11118-11119
- Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten:
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration.
11120-11121
- Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans:
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.
11122-11123
- Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol:
Mapping Applications to an FPFA Tile.
11124-11125
- Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch:
Load Distribution with the Proximity Congestion Awareness in a Network on Chip.
11126-11127
- Adrijean Andriahantenaina, Alain Greiner:
Micro-Network for SoC: Implementation of a 32-Port SPIN network.
11128-11129
- Achim Rettberg, Mauro Cesar Zanella, Christophe Bobda, Thomas Lehmann:
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems.
11130-11131
- Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
Library Functions Timing Characterization for Source-Level Analysis.
11132-11133
- Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer.
11134-11135
- S. F. Nielsen, Jan Madsen:
Power Constrained High-Level Synthesis of Battery Powered Digital Systems.
11136-11137
- Bilge Saglam Akgul, Vincent John Mooney III:
PARLAK: Parametrized Lock Cache Generator.
11138-11139
- Tom J. Kazmierski, Xing Q. Yang:
A Secure Web-Based Framework for Electronic System Level Design.
11140-11143
Low Power Design and Estimation,
Verification and Testing
- Pieter Op de Beeck, C. Ghez, Erik Brockmeyer, Miguel Miranda, Francky Catthoor, Geert Deconinck:
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.
11144-11145
- Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De:
Compiler Support for Reducing Leakage Energy Consumption.
11146-11147
- Peng Rong, Massoud Pedram:
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries.
11148-11149
- Jiong Luo, Li-Shiuan Peh, Niraj K. Jha:
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
11150-11151
- MingHung Lee, TingTing Hwang, Shi-Yu Huang:
Decomposition of Extended Finite State Machine for Low Power Design.
11152-11153
- Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
11154-11155
- Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Using RTL Statespace Information and State Encoding for Induction Based Property Checking.
11156-11157
- Enric Pastor, Marco A. Peña:
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems.
11158-11159
- Naran Sirisantana, Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
11160-11161
- Steffen Tarnick:
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes.
11162-11163
- Petros Drineas, Yiorgos Makris:
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees.
11164-11167
System Level Design and Specification and Testing Techniques
- Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien:
SAT-Based Techniques in System Synthesis.
11168-11169
- Christoph Grimm, Christian Meise, Wilhelm Heupke, Klaus Waldschmidt:
Refinement of Mixed-Signal Systems with SystemC.
11170-11171
- Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet:
Polychrony for Refinement-Based Design.
11172-11173
- Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.
11174-11175
- Ivo Schanstra, A. J. van de Goor:
Consequences of RAM Bitline Twisting for Test Coverage.
11176-11177
- Francesco Corsi, Cristoforo Marzocca, Gianvito Matarrese:
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme.
11178-11179
- Hideyuki Ichihara, Tomoo Inoue:
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG.
11180-11181
- Ondrej Novák:
Comparison of Test Pattern Decompression Techniques.
11182-11183
- Ilia Polian, Bernd Becker, Sudhakar M. Reddy:
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.
11184-11185
- Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Based on Output Dependence.
11186-11187
- Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty:
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization.
11188-11190
Volume II:
Designers' Forum
Design Case Studies
- Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
20002-20007
- Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
20008-20013
- George Lykakis, N. Mouratidis, Kyriakos Vlachos, Nikos A. Nikolaou, Stylianos Perissakis, G. Sourdis, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Dionisios I. Reisis:
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip.
20014-20019
- Alex Panato, Marcelo Barcelos, Ricardo Augusto da Luz Reis:
A Low Device Occupation IP to Implement Rijndael Algorithm.
20020-20025
- Marco Caldari, Massimo Conti, Massimo Coppola, Stephane Curaba, Lorenzo Pieralisi, Claudio Turchetti:
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0.
20026-20031
- Marco Caldari, Massimo Conti, Massimo Coppola, Paolo Crippa, Simone Orcioni, Lorenzo Pieralisi, Claudio Turchetti:
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus.
20032-20039
Embedded Operating Systems for SoC (Embedded Software Forum)
- S. Glaeson, E. Petit:
Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets.
20040
- Monica Besana, Michele Borgatti:
Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study.
20041-20044
- Marek Jersak, Kai Richter, Rolf Ernst, Jörn-Christian Braam, Zheng-Yu Jiang, Fabian Wolf:
Formal Methods for Integration of Automotive Software.
20045-20050
- Frédéric Pétrot, Pascal Gomez:
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect.
20051-20056
- B. Nicolescu, Raoul Velazco:
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results.
20057-20063
Hot Topic:
Network Processing Key Technologies and Architectural Components
- Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane:
Network Processing Challenges and an Experimental NPU Platform.
20064-20069
- Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino:
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network.
20070-20073
- Naresh Soni, Nick Richardson, Lun Bin Huang, Suresh Rajgopal, George Vlantis:
NPSE: A High Performance Network Packet Search Engine.
20074-20081
SystemC Based Design
- Koji Ara, Kei Suzuki:
A Proposal for Transaction-Level Verification with Component Wrapper Language.
20082-20087
- Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates:
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard.
20088-20094
- Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene:
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification.
20095-20100
- Massimo Bombana, Francesco Bruschi:
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain.
20101-20105
- Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia:
IPSIM: SystemC 3.0 Enhancements for Communication Refinement.
20106-20111
- Francesco Bruschi, Fabrizio Ferrandi:
Synthesis of Complex Control Structures from Behavioral SystemC Models.
20112-20119
Embedded Software Design and Implementation (Embedded Software Forum)
- Imed Moussa, Thierry Grellier, Giang Nguyen:
Exploring SW Performance Using SoC Transaction-Level Modeling.
20120-20125
- Marco Göltze:
A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices.
20126-20131
- Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
20132-20137
- Shinya Honda, Hiroaki Takada:
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device.
20138-20143
- Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández:
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys.
20144-20149
- Stephen Jan, Paolo de Dios, Stephen A. Edwards:
Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development.
20150-20157
Design Exploration Methodologies
- Johan Lilius, Dragos Truscan, Seppo Virtanen:
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing.
20158-20163
- Silvia Brini, Doha Benjelloun, Fabien Castanier:
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems.
20164-20169
- Sharath Kodase, Shige Wang, Kang G. Shin:
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints.
20170-20175
- Osamu Ogawa, Sylvain Bayon de Noyer, Pascal Chauvet, Katsuya Shinohara, Yoshiharu Watanabe, Hiroshi Niizuma, Takayuki Sasaki, Yuji Takai:
A Practical Approach for Bus Architecture Optimization at Transaction Level.
20176-20181
- Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.
20182-20187
- Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino:
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture.
20188-20195
Design Methodologies
- Árpád Bürmen, Janez Puhan, Tadej Tuma:
Defining Cost Functions for Robust IC Design and Optimization.
20196-20201
- Martin Schrader, Roderick McConnell:
SoC Design and Test Considerations.
20202-20207
- Bernard Laurent, Thierry Karger:
A System to Validate and Certify Soft and Hard IP.
20208-20213
- Marco Caldari, Massimo Conti, Paolo Crippa, Giuliano Marozzi, Fabio Di Gennaro, Simone Orcioni, Claudio Turchetti:
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel.
20214-20219
- François Rémond, Pierre Bricaud:
Set Top Box SoC Design Methodology at STMicroelectronics.
20220-20223
- Fotis Andritsopoulos, C. Charopoulos, Gregory Doumenis, Fotis Karoubalis, Yannis Mitsos, F. Petreas, Ioanna Theologitou, Stylianos Perissakis, Dionisios I. Reisis:
Verification of a Complex SoC: The PRO3 Case-Study.
20224-20231
System Level Design Case Studies
- Leonardo Mangeruca, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Andrea Pierantoni, Michele Pennese:
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain.
20232-20237
- Matjaz Verderber, Andrej Zemva, Damjan Lampret:
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.
20238-20243
- Jürgen Helmschmidt, Eberhard Schüler, Prashant Rao, Sergio Rossi, Serge di Matteo, Rainer Bonitz:
Reconfigurable Signal Processing in Wireless Terminals.
20244-20249
- Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin:
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration.
20250-20255
- Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer:
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study.
20256-20261
- Alessandro Pirola:
A Solution for Hardware Emulation of Non Volatile Memory Macrocells.
20262-20267
Analogue and Mixed Signal Methodology Design
- Rami Ahola, Daniel Wallner, Marius Sida:
Bluetooth Transceiver Design with VHDL-AMS.
20268-20273
- Pierluigi Daglio, Carlo Roma:
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies.
20274-20279
- Ayman Mounir, Ahmed Mostafa, Maged Fikry:
Automatic Behavioural Model Calibration for Efficient PLL System Verification.
20280-20285
- Uwe Knöchel, Thomas Markwirth, Jürgen Hartung, Ralf Kakerow, Radhakrishna Atukula:
Verification of the RF Subsystem within Wireless LAN System Level Simulation.
20286-20291
- Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, Richard B. Brown:
A Top-Down Microsystems Design Methodology and Associated Challenges .
20292-20296
- Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa:
Synthesis of CMOS Analog Cells Using AMIGO.
20297-20302
Copyright © Thu Nov 5 23:27:51 2009
by Michael Ley (ley@uni-trier.de)
