DATE 2004: Paris, France

Volume 1 - 2 - Designers Forum

Keynote Session

Architectural-Level Power Management

Formal Verification Using Functional and Structural Information

Power, Timing and Diagnosis Constrained Testing

Mixed-Signal Circuits and Systems

Communication-Centric and Source-Level Optimisations for High-Level Synthesis

Panel Session: SystemC and System Verilog: Where do They Fit? Where are They Going?

Low Power Systems and Architectures

Advanced Formal Verification Techniques

New Algorithms for TPG

Optimisation of Memory Hierarchies

Hot Topic - High Security Smartcards

New Directions in Low-Power Design

Advances in SAT

Analogue and High-Frequency Test

Energy Efficient Memory Usage

Hot Topic - How Can System-Level Design Solve the Interconnect Technology Scaling Problem?

System Level Design Methodology

System Level Modelling and Analysis

Advances in SoC Testing

New Issues in Analogue System- and Circuit-Level Performance Modelling

Fabrics and Scheduling for Reconfigurable Computing

Power Aware Design and Synthesis

System Level Design: Case Studies, Exploration and Optimisation

Recent Advances in Digital Systems Simulation

On-Line Testing and Reliability for Nanometer Technologies

Parasitic-Aware Analogue Design

Hardware/Software System Design and Architecture Exploration

Hot Topic - Extremely Low-Power Logic

Interactive Presentations