DATE 2006:
Munich, Germany
Georges G. E. Gielen (Ed.):
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006.
European Design and Automation Association, Leuven, Belgium 2006, ISBN 3-9810801-0-6 
Secure and security systems
- Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectures for efficient face authentication in embedded systems.
1-6
- Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, L. Sportiello:
Software implementation of Tate pairing over GF(2m).
7-11
- Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of regular expression pattern matching circuits on FPGA.
12-17
- Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
18-23
- Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang:
An 830mW, 586kbps 1024-bit RSA chip design.
24-29
- Dmitry Akselrod, Asaf Ashkenazi, Yossi Amon:
Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs.
30-35
Reconfigurable computing
- Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer:
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
36-41
- Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek:
Energy-efficient FPGA interconnect design.
42-47
- Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante:
A new approach to compress the configuration information of programmable devices.
48-51
- Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, Fredy Rivera:
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys).
52-57
- Götz Kappen, Tobias G. Noll:
Application specific instruction processor based implementation of a GNSS receiver on an FPGA.
58-63
- Michael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo:
A methodology for FPGA to structured-ASIC synthesis and verification.
64-69
Specification and verification
- Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti:
Synthesis of system verilog assertions.
70-75
- Ali Habibi, Haja Moinudeen, Sofiène Tahar:
Generating finite state machines from SystemC.
76-81
- Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel:
Flexible specification and application of rule-based transformations in an automotive design flow.
82-87
- Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari:
A mixed-signal verification kit for verification of analogue-digital circuits.
88-93
- Pierluigi Daglio:
A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories.
94-99
- Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello:
Software-friendly HW/SW co-simulation: an industrial case study.
100-105
Wireless communication and networking
- Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla:
Modeling and simulation of mobile gateways interacting with wireless sensor networks.
106-111
- Vassilis Papaefstathiou, Ioannis Papaefstathiou:
A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments.
112-117
- Daniele Lo Iacono, J. Zory, Ettore Messina, Nicolo Piazzese, G. Saia, A. Bettinelli:
ASIP architecture for multi-standard wireless terminals.
118-123
- Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera:
Interconnection framework for high-throughput, flexible LDPC decoders.
124-129
- John Dielissen, Andries Hekstra, Vincent Berg:
Low cost LDPC decoder for DVB-S2.
130-135
- Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò:
3dID: a low-power, low-cost hand motion capture device.
136-141
Hot topic - industrially proving SPIRIT consortium standards for design chain integration
On chip communication networks
- Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis:
Networks on chips for high-end consumer-electronics TV system architectures.
148-153
- Luciano Bononi, Nicola Concer:
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh.
154-159
- Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano:
GALS networks on chip: a new solution for asynchronous delay-insensitive links.
160-165
- Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya:
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.
166-171
- Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer:
STAX: statistical crosstalk target set compaction.
172-177
- Kuo-Hsing Cheng, Yu-lung Lo:
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs.
178-182
Automotive
- Kai Richter, Rolf Ernst:
How OEMs and suppliers can face the network integration challenges.
183-188
- Fabiano Costa Carvalho, Carlos Eduardo Pereira, Elias Teodoro Silva Jr., Edison Pignaton de Freitas:
A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN.
189-194
- G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pasquariello, G. Risaliti, C. Tibaldi:
On the verification of automotive protocols.
195-200
- Federico Baronti, Paolo D'Abramo, Martin Knaipp, Rainer Minixhofer, Roberto Roncella, Roberto Saletti, Martin Schrems, Riccardo Serventi, Verena Vescoli:
FlexRay transceiver in a 0.35 µm CMOS high-voltage technology.
201-205
- Andreas Raabe, Stefan Hochgürtel, Joachim K. Anlauf, Gabriel Zachmann:
Space-efficient FPGA-accelerated collision detection for virtual prototyping.
206-211
- Sergio Saponara, Pierangelo Terreni:
Mixed-signal design of a digital input power amplifier for automotive audio applications.
212-216
Interactive presentations
Media and signal processing
- Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia:
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
221-226
- Sutjipto Arifin, Peter Y. K. Cheung:
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation.
227-232
- Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing.
233-238
- Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang:
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
239-243
- Nicolas Mäding, Jens Leenstra, Juergen Pille, Rolf Sautter, Stefan Büttner, S. Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
244-248
- Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo:
Design and test of fixed-point multimedia co-processor for mobile applications.
249-253
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