DATE 2006: Munich, Germany

Keynote Addresses

• Rene Penning de Vries:
  EDA challenges in the converging application world. 1
  
• Walden C. Rhines:
  Sociology of design and EDA. 2
  

Allocation and scheduling for MPSoCs and NoCs

• Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano:
  Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. 3-8
  
• Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
  Efficient link capacity and QoS design for network-on-chip. 9-14
  
• Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali:
  Supporting task migration in multi-processor systems-on-chip: a feasibility study. 15-20
  

Power grid and large interconnect network analysis

• Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang:
  Time domain model order reduction by wavelet collocation method. 21-26
  
• Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen:
  Large power grid analysis using domain decomposition. 27-32
  
• J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
  Analysis and modeling of power grid transmission lines. 33-38
  
• Baohua Wang, Pinaki Mazumder:
  A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function. 39-44
  

Interactive presentation

• Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
  Large scale RLC circuit analysis using RLCG-MNA formulation. 45-46
  

On-line testing and fault tolerance

• Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff:
  Soft delay error analysis in logic circuits. 47-52
  
• Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang:
  A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. 53-58
  
• Daniele Rossi, Carlo Steiner, Cecilia Metra:
  Analysis of the impact of bus implemented EDCs on on-chip SSN. 59-64
  
• Nektarios Kranitis, Andreas Merentitis, N. Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis:
  Optimal periodic testing of intermittent faults in embedded pipelined processor applications. 65-70
  

Interactive presentation

• Sobeeh Almukhaizim, Yiorgos Makris:
  Berger code-based concurrent error detection in asynchronous burst-mode machines. 71-72
  

Chip design records

• Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
  Two-phase resonant clocking for ultra-low-power hearing aid applications. 73-78
  
• Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo:
  A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. 79-80
  
• Cristiano Niclass, Maximilian Sergio, Edoardo Charbon:
  A single photon avalanche diode array fabricated in deep-submicron CMOS technology. 81-86
  

Model based design and test

• Jon Friedman:
  MATLAB/Simulink for automotive systems design. 87-88
  
• Mirko Conrad, Heiko Dörr:
  Model-based development of in-vehicle software. 89-90
  
• Klaus Lamberg:
  Model-based testing of automotive electronics. 91
  
• John Heighton:
  Designing signal processing systems for FPGAs. 92
  
• Yves Vanderperren, Wim Dehaene:
  From UML/SysML to Matlab/Simulink: current state and future perspectives. 93
  

Transaction level modelling based validation

• Emmanuel Viaud, François Pêcheux, Alain Greiner:
  An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. 94-99
  
• Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington:
  Exploiting TLM and object introspection for system-level simulation. 100-105
  
• Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed:
  Efficient assertion based verification using TLM. 106-111
  
• Joseph D'Errico, Wei Qin:
  Constructing portable compiled instruction-set simulators: an ADL-driven approach. 112-117
  

Application-specific network on chip design

• Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli:
  A methodology for mapping multiple use-cases onto networks on chips. 118-123
  
• Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo:
  Contrasting a NoC and a traditional interconnect fabric with layout awareness. 124-129
  
• Krishnan Srinivasan, Karam S. Chatha:
  A low complexity heuristic for design of custom network-on-chip architectures. 130-135
  

Interactive presentation

• Thilo Pionteck, Carsten Albrecht, Roman Koch:
  A dynamically reconfigurable packet-switched network-on-chip. 136-137
  

Methods and tools for systematic analogue design

• Vahid Majidzadeh, Omid Shoaei:
  Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. 138-143
  
• Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez:
  Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation. 144-149
  
• Gerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain:
  Systematic stability-analysis method for analog circuits. 150-155
  
• Hui Zhang, Yang Zhao, Alex Doboli:
  ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. 156-161
  

Interactive presentation

• V. Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto:
  A synthesis tool for power-efficient base-band filter design. 162-163
  

Soft error analysis and concurrent testing

• Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester:
  An efficient static algorithm for computing the soft error rates of combinational circuits. 164-169
  
• Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
  Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. 170-175
  
• Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus:
  Evaluating coverage of error detection logic for soft errors using formal methods. 176-181
  
• N. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nicolescu:
  Soft-error classification and impact analysis on real-time operating systems. 182-187
  

System design records

• H. Shrikumar:
  40Gbps de-layered silicon protocol engine for TCP record. 188-193
  
• Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller:
  A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. 194-199
  
• Torben Brack, Frank Kienle, Norbert Wehn:
  Disclosing the LDPC code decoder design space. 200-205
  

Application-specific architectures

• Robert G. Dimond, Oskar Mencer, Wayne Luk:
  Automating processor customisation: optimised memory access and resource sharing. 206-211
  
• Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
  Automatic identification of application-specific functional units with architecturally visible storage. 212-217
  
• Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma:
  Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. 218-223
  
• Ahmad Zmily, Christos Kozyrakis:
  Simultaneously improving code size, performance, and energy in embedded processors. 224-229
  

System level performance analysis

• Gunar Schirner, Rainer Dömer:
  Quantitative analysis of transaction level models for the AMBA bus. 230-235
  
• Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele:
  Combining simulation and formal methods for system-level performance analysis. 236-241
  
• Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel:
  Formal performance analysis and simulation of UML/SysML models for ESL design. 242-247
  
• Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf:
  Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. 248-253
  

Hot topic - 'Network': the Next 'Big Idea' in design? network paradigms in systems, sensors, and silicon

• Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
  Is "Network" the next "Big Idea" in design? 254-256
  

Advances in verification and synthesis for analogue design automation

• Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar:
  Verifying analog oscillator circuits using forward/backward abstraction refinement. 257-262
  
• Ting Mei, Jaijeet S. Roychowdhury:
  Efficient AC analysis of oscillators using least-squares methods. 263-268
  
• Trent McConaghy, Georges G. E. Gielen:
  Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. 269-274
  
• Ewout Martens, Georges G. E. Gielen:
  Top-down heterogeneous synthesis of analog and mixed-signal systems. 275-280
  

Interactive presentation

• Jose A. Martinez, Steven P. Levitan, Donald M. Chiarulli:
  Nonlinear model order reduction using remainder functions. 281-282
  
• Huiying Yang, Ranga Vemuri:
  Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. 283-284
  

Advanced SoC test scheduling

• Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
  Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. 285-290
  
• Zhiyuan He, Zebo Peng, Petru Eles:
  Power constrained and defect-probability driven SoC test scheduling with test set partitioning. 291-296
  
• Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
  Power-constrained test scheduling for multi-clock domain SoCs. 297-302
  
• Chunsheng Liu, Zach Link, Dhiraj K. Pradhan:
  Reuse-based test access and integrated test scheduling for network-on-chip. 303-308
  

Interactive presentation

• Sandip Kundu:
  A design for failure analysis (DFFA) technique to ensure incorruptible signatures. 309-310
  

Design methodologies for emerging technologies

• Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
  Test generation for combinational quantum cellular automata (QCA) circuits. 311-316
  
• Afshin Abdollahi, Massoud Pedram:
  Analysis and synthesis of quantum circuits by using quantum decision diagrams. 317-322
  
• Fei Su, William L. Hwang, Krishnendu Chakrabarty:
  Droplet routing in the synthesis of digital microfluidic biochips. 323-328
  
• Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Priority scheduling in digital microfluidics-based biochips. 329-334
  

Interactive presentation

• Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie Taylor, Paul Graham, Maya Gokhale:
  A hybrid framework for design and analysis of fault-tolerant architectures. 335-336
  
• Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim:
  Optical routing for 3D system-on-package. 337-338
  

Processor and memory design

• Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest:
  Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. 339-344
  
• Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven:
  Compositional, efficient caches for a chip multi-processor. 345-350
  
• Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere:
  Efficient design space exploration of high performance embedded out-of-order processors. 351-356
  
• Hans Vandierendonck, Philippe Manet, Jean-Didier Legat:
  Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. 357-362
  

Spatial and temporal mapping for reconfigurable computing

• Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi:
  A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. 363-368
  
• Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
  Compiler-driven FPGA-area allocation for reconfigurable computing. 369-374
  
• Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima:
  Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures. 375-380
  
• Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay:
  System-level scheduling on instruction cell based reconfigurable systems. 381-386
  

DFM/DFY design for manufacturability and yield

• Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp:
  DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. 387-392
  

Analogue and mixed-signal design

• Ying Wei, Hua Tang, Alex Doboli:
  Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. 393-398
  
• Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez:
  Double-sampling single-loop sigma-delta modulator topologies for broadband applications. 399-404
  
• Kambiz K. Moez, Mohamed I. Elmasry:
  A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process. 405-409
  

Interactive presentation

• José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi:
  Bootstrapped full--swing CMOS driver for low supply voltage operation. 410-411
  

Processor self-test and fault diagnosis

• Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
  An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. 412-417
  
• Kai Yang, Kwang-Ting Cheng:
  Timing-reasoning-based delay fault diagnosis. 418-423
  
• Yung-Chieh Lin, Kwang-Ting Cheng:
  Multiple-fault diagnosis based on single-fault activation and single-output observation. 424-429
  
• Jun Zhou, Hans-Joachim Wunderlich:
  Software-based self-test of processors under power constraints. 430-435
  

Interactive presentation

• Yu Huang, Keith Gallie:
  Diagnosis of defects on scan enable and clock trees. 436-437
  

Scheduling for real-time and energy

• Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen:
  Lock-free synchronization for dynamic embedded real-time systems. 438-443
  
• Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele:
  Performance analysis of greedy shapers in real-time systems. 444-449
  
• Rafik Henia, Rolf Ernst:
  Improved offset-analysis using multiple timing-references. 450-455
  
• Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron:
  Procrastinating voltage scheduling with discrete frequency sets. 456-461
  

System level modelling and simulation

• Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli:
  Communication and co-simulation infrastructure for heterogeneous system integration. 462-467
  
• Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
  A SW performance estimation framework for early system-level-design using fine-grained instrumentation. 468-473
  
• Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez:
  A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study. 474-479
  

Interactive presentation

• Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf:
  Task-accurate performance modeling in SystemC for real-time multi-processor architectures. 480-481
  

Hot topic: system level design of SoC (4G wireless special day)

• Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo:
  Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. 482-487
  
• Tim Kogel, Matthew Braun:
  Virtual prototyping of embedded platforms for wireless and multimedia. 488-490
  
• Luca Benini:
  Application specific NoC design. 491-495
  

Power-efficient hardware/software architectures

• Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.:
  Automatic insertion of low power annotations in RTL for pipelined microprocessors. 496-501
  
• Bren Mochocki, Kanishka Lahiri, Srihari Cadambi:
  Power analysis of mobile 3D graphics. 502-507
  
• Nathaniel Pettis, Jason Ridenour, Yung-Hsiang Lu:
  Automatic run-time selection of power policies for operating systems. 508-513
  
• Changjiu Xian, Yung-Hsiang Lu:
  Energy reduction by workload adaptation in a multi-process environment. 514-519
  

Interactive presentation

• Jongsun Park, Jung Hwan Choi, Kaushik Roy:
  Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. 520-521
  

Timing and noise analysis

• Brock J. LaMeres, Sunil P. Khatri:
  Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. 522-527
  
• Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
  Statistical timing analysis with path reconvergence and spatial correlations. 528-532
  
• Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
  Non-gaussian statistical interconnect timing analysis. 533-538
  
• Shahin Nazarian, Massoud Pedram:
  Cell delay analysis based on rate-of-current change. 539-544
  

Interactive presentation

• Frank Liu:
  A practical method to estimate interconnect responses to variabilities. 545-546
  

Test and reliability challenges in automotive microelectronics

• C. Sebeke, C. Jung, Klaus Harbich, S. Fuchs, J. Schwarz, Peter Göhner:
  Test and reliability challenges in automotive microelectronics. 547
  

Communication methods and networking in automotive systems

• Sri Kanajan, Haibo Zeng, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli:
  Exploring trade-off's between centralized versus decentralized automotive architectures using a virtual integration environment. 548-553
  
• Thomas Weber:
  Management of complex automotive communication networks. 554-555
  
• Andreas Herkersdorf, Walter Stechele:
  AutoVision: flexible processor architecture for video-assisted driving. 556
  
• Klaus D. Müller-Glaser:
  Domain specific model driven design for automotive electronic control units. 557
  
• Pascal Dégardins:
  Electric and electronic vehicle architecture assessment. 558
  
• Patrick Leteinturier:
  Automotive semi-conductor trend & challenges. 559
  

System level modelling

• Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
  A systematic IP and bus subsystem modeling for platform-based system design. 560-564
  
• Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi:
  Heterogeneous behavioral hierarchy for system level designs. 565-570
  
• Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede:
  Design with race-free hardware semantics. 571-576
  

Interactive presentation

• Steffen Prochnow, Reinhard von Hanxleden:
  Comfortable modeling of complex reactive systems. 577-578
  
• Waseem Ahmed, Doug Myers:
  Faster exploration of high level design alternatives using UML for better partitions. 579-580
  

Hot topic: architectures and NoC (4G wireles special day)

• Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey:
  A design flow for configurable embedded processors based on optimized instruction set extension synthesis. 581-586
  
• Pablo Robelly, Hendrik Seidel, K. C. Chen, Gerhard Fettweis:
  Energy efficiency vs. programmability trade-off: architectures and design principles. 587-592
  
• Andreas Burg, Moritz Borgmann, Markus Wenk, Christoph Studer, Helmut Bölcskei:
  Advanced receiver algorithms for MIMO wireless communications. 593-598
  

Keynote

• D. Shaver:
  Next generation architectures can dramatically reduce the 4G deployment cycle. 599
  

Low power embedded architectures and platforms

• Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  Automatic ADL-based operand isolation for embedded processors. 600-605
  
• Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
  Power/performance hardware optimization for synchronization intensive applications in MPSoCs. 606-611
  
• Akhilesh Kumar, Mohab Anis:
  An analytical state dependent leakage power model for FPGAs. 612-617
  
• Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
  Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. 618-623
  

Interactive presentation

• Krishnan Sundaresan, Nihar R. Mahapatra:
  Value-based bit ordering for energy optimization of on-chip global signal buses. 624-625
  

Transistor and gate level simulation

• Jayashree Sridharan, Tom Chen:
  Modeling multiple input switching of CMOS gates in DSM technology using HDMR. 626-631
  
• Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner:
  A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. 632-637
  
• Peter M. Maurer:
  Using conjugate symmetries to enhance gate-level simulations. 638-643
  

Interactive presentation

• Hessa Al-Junaid, Tom J. Kazmierski:
  HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope. 644-645
  

SoC targeted mixed-signal test solutions

• Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
  An improved RF loopback for test time reduction. 646-651
  
• Chunsheng Liu, Vikram Iyengar:
  Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. 652-657
  
• Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee:
  Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms. 658-663
  
• Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur:
  Pseudorandom functional BIST for linear and nonlinear MEMS. 664-669
  

Interactive presentation

• Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
  On-chip 8GHz non-periodic high-swing noise detector. 670-671
  

System optimisation with embedded software

• Anirban Lahiri, Anupam Basu, Monojit Choudhury, Srobona Mitra:
  Battery-aware code partitioning for a text to speech system. 672-677
  
• Zhongwen Li, Hong Chen, Shui Yu:
  Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems. 678-683
  
• Radu Cornea, Alexandru Nicolau, Nikil D. Dutt:
  Software annotations for power optimization on mobile devices. 684-689
  
• Liping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu:
  Dynamic partitioning of processing and memory resources in embedded MPSoC architectures. 690-695
  

Interactive presentation

• Mahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu:
  Activity clustering for leakage management in SPMs. 696-697
  
• Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan:
  Adaptive data placement in an embedded multiprocessor thread library. 698-699
  

Communication-centric system-level synthesis for MPSoC

• Sudeep Pasricha, Nikil D. Dutt:
  COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. 700-705
  
• Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng:
  Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems. 706-711
  
• Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Naehyuck Chang:
  Communication architecture optimization: making the shortest path shorter in regular networks-on-chip. 712-717
  
• Sorin Manolache, Petru Eles, Zebo Peng:
  Buffer space optimisation with communication synthesis and traffic shaping for NoCs. 718-723
  

Interactive presentation

• Kuan Jen Lin, Shih Hao Huang, Shan Chien Fang:
  Cooptimization of interface hardware and software for I/O controllers. 724-725
  

Hot topic: cross disciplinary aspects (4G wireless special day)

• Tobias G. Noll, Uwe Lambrette:
  Cross disciplinary aspects (4G wireless special day). 726
  
• Uwe Lambrette, Booz Allen Hamilton:
  SoC: fuelling the hopes of the mobile industry. 727
  

Techniques for architecture exploration and characterisation

• Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
  Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. 728-733
  
• Douglas Densmore, Adam Donlin, Alberto L. Sangiovanni-Vincentelli:
  FPGA architecture characterization for system level performance analysis. 734-739
  
• Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis:
  Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. 740-745
  
• Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran:
  Customization of application specific heterogeneous multi-pipeline processors. 746-751
  

Interactive presentation

• Benny Thörnberg, Mattias O'Nils:
  Impact of bit-width specification on the memory hierarchy for a real-time video processing system. 752-753
  
• Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar:
  Efficient factorization of DSP transforms using taylor expansion diagrams. 754-755
  

Clocks and routing

• Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze:
  Integrated placement and skew optimization for rotary clocking. 756-761
  
• Min-Seok Kim, Jiang Hu:
  Associative skew clock routing for difficult instances. 762-767
  
• Shantanu Dutt, Hasan Arslan:
  Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. 768-773
  

Reliability issues for nanotechnology circuits

• Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi:
  Defect tolerance of QCA tiles. 774-779
  
• Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
  Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. 780-785
  
• Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli:
  Novel designs for thermally robust coplanar crossing in QCA. 786-791
  

Interactive presentation

• Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
  Designing MRF based error correcting circuits for memory elements. 792-793
  

Architectures for predictable real-time computing and communication

• Klaus Steinhammer, Petr Grillinger, Astrit Ademaj, Hermann Kopetz:
  A time-triggered ethernet (TTE) switch. 794-799
  
• Martin Schoeberl:
  A time predictable Java processor. 800-805
  
• Marco A. Wehrmeister, Carlos Eduardo Pereira, Leandro Buss Becker:
  Optimizing the generation of object-oriented real-time embedded applications based on the real-time specification for Java. 806-811
  

Modern decision procedures

• Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella:
  Quantifier structure in search based procedures for QBFs. 812-817
  
• HoonSang Jin, Fabio Somenzi:
  Strong conflict analysis for propositional satisfiability. 818-823
  
• Namrata Shekhar, Priyank Kalla, Florian Enescu:
  Equivalence verification of arithmetic datapaths with multiple word-length operands. 824-829
  

Applications, architectures, design methodology and tools for MPSoc

• 4G applications, architectures, design methodology and tools for MPSoC. 830-831
  

Thermal aspects of low power design

• Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino:
  Thermal resilient bounded-skew clock tree optimization methodology. 832-837
  
• Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini:
  Exploring "temperature-aware" design in low-power MPSoCs. 838-843
  
• Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick:
  Adaptive chip-package thermal analysis for synthesis and design. 844-849
  
• Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
  On-chip bus thermal analysis and optimization. 850-855
  

Leakage and dynamic power aware logic design

• Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
  Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. 856-861
  
• Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia:
  Low power synthesis of dynamic logic circuits using fine-grained clock gating. 862-867
  
• Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii:
  Enabling fine-grain leakage management by voltage anchor insertion. 868-873
  

Interactive presentation

• Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
  Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. 874-875
  
• Andrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano:
  A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs. 876-877
  

Advanced topics in physical design

• Eric Wong, Sung Kyu Lim:
  3D floorplanning with thermal vias. 878-883
  
• Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
  Timing-driven cell layout de-compaction for yield optimization by critical area minimization. 884-889
  
• Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
  Lens aberration aware timing-driven placement. 890-895
  

Advances in defect modelling and detection

• Bram Kruseman, Manuel Heiligers:
  On test conditions for the detection of open defects. 896-901
  
• José Luis Rosselló, Jaume Segura:
  A compact model to identify delay faults due to crosstalk. 902-906
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Generation of broadside transition fault test sets that detect four-way bridging faults. 907-912
  
• Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton:
  Extraction of defect density and size distributions from wafer sort test results. 913-918
  

Code and data layout optimisations for embedded software

• Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  An interprocedural code optimization technique for network processors using hardware multi-threading support. 919-924
  
• Sumesh Udayakumaran, Rajeev Barua:
  An integrated scratch-pad allocator for affine and non-affine code. 925-930
  
• Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy:
  Dynamic scratch-pad memory management for irregular array access patterns. 931-936
  
• Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo Han:
  Restructuring field layouts for embedded memory systems. 937-942
  

Interactive presentation

• Po-Kuan Huang, Soheil Ghiasi:
  Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. 943-944
  
• Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha:
  Dynamic code overlay of SDF-modeled programs on low-end embedded systems. 945-946
  

Advanced reconfigurable architectures and applications

• Balasubramanian Sethuraman, Ranga Vemuri:
  optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. 947-952
  
• Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley:
  Hardware efficient architectures for Eigenvalue computation. 953-958
  
• Chidamber Kulkarni, Gordon J. Brebner:
  Memory centric thread synchronization on platform FPGAs. 959-964
  
• Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
  A parallel configuration model for reducing the run-time reconfiguration overhead. 965-969
  

Hot topic - introduction to and applications for wireless sensor networks (WSN) - (wireless sensor networks special day)

• Paul J. M. Havinga:
  Wireless sensor networks and beyond. 970
  
• Amre El-Hoiydi, Claude Arm, R. Caseiro, Stefan Cserveny, Jean-Dominique Decotignie, Christian C. Enz, F. Giroud, S. Gyger, E. Leroux, Thierry Melly, Vincent Peiris, F. Pengg, P.-D. Pfister, N. Raemy, A. Ribordy, D. Ruffieux, P. Volet:
  The ultra low-power wiseNET system. 971-976
  
• Jan Beutel:
  Fast-prototyping using the BTnode platform. 977-982
  

Leakage-aware circuit design

• Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy:
  Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. 983-988
  
• Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine:
  Architectural and technology influence on the optimal total power consumption. 989-994
  
• Behnam Amelifard, Farzan Fallah, Massoud Pedram:
  Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. 995-1000
  
• Kaushal R. Gandhi, Nihar R. Mahapatra:
  Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. 1001-1006
  

Coverage based validation

• Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
  On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. 1007-1012
  
• Felice Balarin, Roberto Passerone:
  Functional verification methodology based on formal interface specification and transactor generation. 1013-1018
  
• Ian G. Harris:
  A coverage metric for the validation of interacting processes. 1019-1024
  
• Vasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar Müller:
  New methods and coverage metrics for functional verification. 1025-1030
  

Interactive presentation

• Alexander Krupp, Wolfgang Müller:
  Classification trees for random tests and functional coverage. 1031-1032
  

Test data compression

• Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
  Efficient test-data compression for IP cores using multilevel Huffman coding. 1033-1038
  
• Ilia Polian, Hideo Fujiwara:
  Functional constraints vs. test compression in scan-based delay testing. 1039-1044
  
• Gang Zeng, Hideo Ito:
  Concurrent core test for SOC using shared test set and scan chain disable. 1045-1050
  

Interactive presentations

• Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar:
  Efficient unknown blocking using LFSR reseeding. 1051-1052
  
• Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng:
  Coverage loss by using space compactors in presence of unknown values. 1053-1054
  

Resource constrained scheduling

• Hui Cheng, Steve Goddard:
  Online energy-aware I/O device scheduling for hard real-time systems. 1055-1060
  
• Heng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo:
  Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint. 1061-1066
  
• Hadda Cherroun, Alain Darte, Paul Feautrier:
  Scheduling under resource constraints using dis-equations. 1067-1072
  
• Zhe Ma, Francky Catthoor:
  Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms. 1073-1078
  

Sequential optimisation, clocking and Boolean matching

• Donald Chai, Andreas Kuehlmann:
  Building a better Boolean matcher and symmetry detector. 1079-1084
  
• Cristian Soviani, Olivier Tardieu, Stephen A. Edwards:
  Optimizing sequential cycles through Shannon decomposition and retiming. 1085-1090
  
• Christoph Albrecht:
  Efficient incremental clock latency scheduling for large circuits. 1091-1096
  
• Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai:
  Analyzing timing uncertainty in mesh-based clock architectures. 1097-1102
  

Hot topic - design, verification, deployment and test of WSN systems

• Alvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
  Platform-based design of wireless sensor networks for industrial applications. 1103-1107
  
• Vlado Handziski, Andreas Köpke, Andreas Willig, Adam Wolisz:
  An environment for controlled experiments with in-house sensor networks. 1108
  

Keynote

• Philippe Bonnet, Martin Leopold, K. Madsen:
  Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day). 1109
  

Power reduction at circuit level

• Lakshmi N. Chakrapani, Bilge E. S. Akgul, Suresh Cheemalavagu, Pinar Korkmaz, Krishna V. Palem, Balasubramanian Seshasayee:
  Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology. 1110-1115
  
• Mark M. Budnik, Kaushik Roy:
  Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. 1116-1121
  
• Yen-Jen Chang:
  An ultra low-power TLB design. 1122-1127
  
• Peng Rong, Massoud Pedram:
  Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms. 1128-1133
  

Semi-formal validation methods

• David W. Matula, Lee D. McFearin:
  A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division. 1134-1138
  
• Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
  On the relation between simulation-based and SAT-based diagnosis. 1139-1144
  
• Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini:
  An integrated open framework for heterogeneous MPSoC design space exploration. 1145-1150
  
• Dohyung Kim, Soonhoi Ha, Rajesh Gupta:
  Parallel co-simulation using virtual synchronization with redundant host execution. 1151-1156
  

Interactive presentation

• Hiroaki Nakamura, Naoto Sato, Naoshi Tabuchi:
  An efficient and portable scheduler for RTOS simulation and its certified integration to SystemC. 1157-1158
  

Testing memories, FPGAs and networks-on-a-chip

• Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
  Minimizing test power in SRAM through reduction of pre-charge activity. 1159-1164
  
• Vishal Suthar, Shantanu Dutt:
  Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. 1165-1170
  
• Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi:
  A concurrent testing method for NoC switches. 1171-1176
  

Interactive presentation

• David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
  A secure scan design methodology. 1177-1178
  

Architectural level synthesis

• Chen He, Margarida F. Jacome:
  RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics. 1179-1184
  
• Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh:
  Layout driven data communication optimization for high level synthesis. 1185-1190
  
• Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos:
  Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. 1191-1196
  
• Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek:
  Automatic generation of operation tables for fast exploration of bypasses in embedded processors. 1197-1202
  

Interactive presentation

• Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra:
  High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. 1203-1204
  

Advances in state space exploration

• Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta:
  Disjunctive image computation for embedded software verification. 1205-1210
  
• Smitha Shyam, Valeria Bertacco:
  Distance-guided hybrid verification with GUIDO. 1211-1216
  
• Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti:
  What lies between design intent coverage and model checking? 1217-1222
  

Interactive presentations

• Jounaïdi Ben Hassen, Sofiène Tahar:
  On the numerical verification of probabilistic rewriting systems. 1223-1224
  
• Görschwin Fey, Daniel Große, Rolf Drechsler:
  Avoiding false negatives in formal verification for protocol-driven blocks. 1225-1226
  

Low-power design tools: are EDA vendors taking this matter seriously?

• Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon:
  Low-power design tools: are EDA vendors taking this matter seriously? 1227
  

System level verification

• Daniel Karlsson, Petru Eles, Zebo Peng:
  Formal verification of systemc designs using a petri-net based representation. 1228-1233
  
• Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan:
  Monolithic verification of deep pipelines with collapsed flushing. 1234-1239
  
• Heon-Mo Koo, Prabhat Mishra:
  Functional test generation using property decompositions for validation of pipelined processors. 1240-1245
  
• Katell Morin-Allory, Dominique Borrione:
  Proven correct monitors from PSL specifications. 1246-1251
  

Memory testing and test set improvement

• Zaid Al-Ars, Said Hamdioui, A. J. van de Goor:
  Space of DRAM fault models and corresponding testing. 1252-1257
  
• Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
  Automatic march tests generations for static linked faults in SRAMs. 1258-1263
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Test compaction for transition faults under transparent-scan. 1264-1269
  
• Zhanglei Wang, Krishnendu Chakrabarty, Michael Gössel:
  Test set enrichment using a probabilistic fault model and the theory of output deviations. 1270-1275
  

Reliable microarchitectures

• Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli:
  Vulnerability analysis of L2 cache elements to single event upsets. 1276-1281
  
• Soontae Kim:
  Area-efficient error protection for caches. 1282-1287
  
• Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
  Microarchitectural floorplanning under performance and thermal tradeoff. 1288-1293
  

Progress in logic and arithmetic circuit optimisation

• Anup Hosangadi, Farzan Fallah, Ryan Kastner:
  Optimizing high speed arithmetic circuits using three-term extraction. 1294-1299
  
• Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
  Efficient minimization of fully testable 2-SPP networks. 1300-1305
  
• Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
  Pre-synthesis optimization of multiplications to improve circuit performance. 1306-1311
  
• Yi-Yu Liu, TingTing Hwang:
  Crosstalk-aware domino logic synthesis. 1312-1317
  

MPSoC modelling and design

• Wolfgang Klingauf, Hagen Gädke, Robert Günzel:
  TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. 1318-1323
  
• Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen:
  Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications. 1324-1329
  
• Olivier Muller, Amer Baghdadi, Michel Jézéquel:
  ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. 1330-1335