DATE 2009:
Nice, France
Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009.
IEEE 2009
- Mike Muller:
Has anything changed in electronic design since 1983?
1

- Joseph Sifakis:
Embedded systems design - Scientific challenges and work directions.
2

- Huaxi Gu, Jiang Xu, Wei Zhang:
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
3-8

- Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.
9-14

- Chen-Ling Chou, Radu Marculescu:
User-centric design space exploration for heterogeneous Network-on-Chip platforms.
15-20

- David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw:
A highly resilient routing algorithm for fault-tolerant NoCs.
21-26

- Sean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram Putzke-Röming:
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture.
27-32

- Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan:
An ILP formulation for task mapping and scheduling on multi-core architectures.
33-38

- Wenxue Gao, Andreas Kugel, Reinhard Männer, Norbert Abel, Nick Meier, Udo Kebschull:
DPR in high energy physics.
39-44

- Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
A flexible layered architecture for accurate digital baseband algorithm development and verification.
45-50

- Lin Huang, Feng Yuan, Qiang Xu:
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms.
51-56

- Soheil Samii, Anton Cervin, Petru Eles, Zebo Peng:
Integrated scheduling and synthesis of control applications on distributed embedded systems.
57-62

- Chengmo Yang, Alex Orailoglu:
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude.
63-68

- Hoeseok Yang, Soonhoi Ha:
Pipelined data parallel task mapping/scheduling technique for MPSoC.
69-74

- Kai-Chiang Wu, Diana Marculescu:
Joint logic restructuring and pin reordering against NBTI-induced performance degradation.
75-80

- Omer Khan, Sandip Kundu:
A self-adaptive system architecture to address transistor aging.
81-86

- Mihir R. Choudhury, Kartik Mohanram:
Masking timing errors on speed-paths in logic circuits.
87-92

- Michael Mendler, Reinhard von Hanxleden, Claus Traulsen:
WCRT algebra and interfaces for esterel-style synchronous processing.
93-98

- Nikolay Stoimenov, Simon Perathoner, Lothar Thiele:
Reliable mode changes in real-time systems with fixed priority or EDF scheduling.
99-104

- Victor Pollex, Steffen Kollmann, Karsten Albers, Frank Slomka:
Improved worst-case response-time calculations by upper-bound conditions.
105-110

- William Plishker, Nimish Sane, Shuvra S. Bhattacharyya:
A generalized scheduling approach for dynamic dataflow applications.
111-116

- Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon:
Optimizing data flow graphs to minimize hardware implementation.
117-122

- Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic:
Multi-clock Soc design using protocol conversion.
123-128

- Karin Avnit, Arcot Sowmya:
A formal approach to design space exploration of protocol converters.
129-134

- Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich:
Model-based synthesis and optimization of static multi-rate image processing algorithms.
135-140

- Marco Casale-Rossi, Giovanni De Micheli:
Panel session - Consolidation, a modern "Moor of Venice" tale.
141

- Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski:
Variation resilient adaptive controller for subthreshold circuits.
142-147

- David R. Bild, Gregory E. Bok, Robert P. Dick:
Minimization of NBTI performance degradation using internal node control.
148-153

- Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii:
Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
154-159

- Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks:
An event-guided approach to reducing voltage noise in processors.
160-165

- Panagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos:
Design and implementation of a database filter for BLAST acceleration.
166-171

- Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris:
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.
172-177

- Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Priority-based packet communication on a bus-shaped structure for FPGA-systems.
178-183

- Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres:
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
184-189

- Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe:
Functional qualification of TLM verification.
190-195

- Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley:
Solver technology for system-level to RTL equivalence checking.
196-201

- Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad:
A high-level debug environment for communication-centric debug.
202-207

- Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Cache aware compression for processor debug support.
208-213

- Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss:
Fault insertion testing of a novel CPLD-based fail-safe system.
214-219

- Li Jiang, Lin Huang, Qiang Xu:
Test architecture design and optimization for three-dimensional SoCs.
220-225

- Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Philippe Soulard, Jean-Philippe Diguet:
A co-design approach for embedded system modeling and code generation with UML and MARTE.
226-231

- Kecheng Hao, Fei Xie:
Componentizing hardware/software interface design.
232-237

- Tim Schattkowsky, Tao Xie, Wolfgang Müller:
A UML frontend for IP-XACT-based IP management.
238-243

- Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA.
244-249

- Andreas Hansson, Mahesh Subburaman, Kees Goossens:
Aelite: A flit-synchronous Network on Chip with composable and predictable services.
250-255

- Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel:
Configurable links for runtime adaptive on-chip communication.
256-261

- Igor Loi, Federico Angiolini, Luca Benini:
Synthesis of low-overhead configurable source routing tables for network interfaces.
262-267

- Abelardo Jara-Berrocal, Ann Gordon-Ross:
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems.
268-273

- Helmut Gräb, Florin Balasa, R. Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser:
Analog layout synthesis - Recent advances in topological approaches.
274-279

- Baohua Wang, Pinaki Mazumder:
An accurate interconnect thermal model using equivalent transmission line circuit.
280-283

- Tobias Kirchner, Nico Bannow, Christoph Grimm:
Analogue mixed signal simulation using spice and SystemC.
284-287

- Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen:
Reliability aware through silicon via planning for 3D stacked ICs.
288-291

- Kelageri Nagaraj, Sandip Kundu:
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation.
292-295

- Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan:
Analysis and optimization of NBTI induced clock skew in gated clock trees.
296-299

- Adam Flynn, Ann Gordon-Ross, Alan D. George:
Bitstream relocation with local clock domains for partially reconfigurable FPGAs.
300-303

- He Peng, Chung-Kuan Cheng:
Parallel transistor level full-chip circuit simulation.
304-307

- Fu-Wei Chen, Yi-Yu Liu:
Performance-driven dual-rail insertion for chip-level pre-fabricated design.
308-311

- Martin Trautmann, Stylianos Mamagkakis, Bruno Bougard, Jeroen Declerck, Erik Umans, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor:
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning.
312-315

- H. W. M. van Moll, Henk Corporaal, Víctor Reyes, Marleen Boonen:
Fast and accurate protocol specific bus modeling using TLM 2.0.
316-319

- Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Incorporating graceful degradation into embedded system design.
320-323

- Chun-Chi Lin, Chun-Yao Wang:
Rewiring using IRredundancy Removal and Addition.
324-327

- Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Gate replacement techniques for simultaneous leakage and aging optimization.
328-333

- Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow.
334-339

- Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir:
TRAM: A tool for Temperature and Reliability Aware Memory Design.
340-345

- Jean Casteres, Tovo Ramaherirariny:
Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs.
346-351

- Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
352-357

- Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozbeh Jafari:
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique.
358-363

- Luca Larcher, Riccardo Brama, Marcello Ganzerli, Jacopo Iannacci, Marco Bedani, Antonio Gnudi:
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard.
364-368

- José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramó Ruiz-Merino:
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
369-373

- Loic Le Toumelin:
PANEL SESSION - Is the second wave of HLS the one industry will surf on?
374

- Sherief Reda, Sani R. Nassif:
Analyzing the impact of process variations on parametric measurements: Novel models and applications.
375-380

- Aswin Sreedhar, Sandip Kundu:
On linewidth-based yield analysis for nanometer lithography.
381-386

- Vikas Chandra, Robert C. Aitken:
Impact of voltage scaling on nanoscale SRAM reliability.
387-392

- Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo:
A file-system-aware FTL design for flash-memory storage systems.
393-398

- Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis:
FSAF: File system aware flash translation layer for NAND Flash Memories.
399-404

- Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei-Wei Kuo:
A set-based mapping strategy for flash-memory reliability enhancement.
405-410

- Jason Cong, Karthik Gururaj:
Energy efficient multiprocessor task scheduling under input-dependent variation.
411-416

- Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling.
417-422

- Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
423-428

- P. Parrish:
PANEL SESSION - Open source hardware IP, are you serious?
429

- Lorena Anghel:
HOT TOPIC - Concurrent SoC development and end-to-end planning.
430

- Shinobu Fujita:
Nano-electronics challenge chip designers meet real nano-electronics in 2010s?
431-432

- Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues.
433-435

- Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei:
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
436-441

- Chen Dong, Scott Chilstedt, Deming Chen:
Reconfigurable circuit design with nanomaterials.
442-447

- Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
An architecture for secure software defined radio.
448-453

- Xu Guo, Patrick Schaumont:
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage.
454-459

- Foad Dabiri, Miodrag Potkonjak:
Hardware aging-based software metering.
460-465

- Young-Pyo Joo, Sungchan Kim, Soonhoi Ha:
On-chip communication architecture exploration for processor-pool-based MPSoC.
466-471

- Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich:
Combined system synthesis and communication architecture exploration for MPSoCs.
472-477

- Douglas Densmore, Alena Simalatsar, Abhijit Davare, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
UMTS MPSoC design evaluation using a system level design framework.
478-483

- Mikael Väyrynen, Virendra Singh, Erik Larsson:
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips.
484-489

- Abhisek Pan, Omer Khan, Sandip Kundu:
Improving yield and reliability of chip multiprocessors.
490-495

- Guihai Yan, Yinhe Han, Xiaowei Li:
A unified online Fault Detection scheme via checking of Stability Violation.
496-501

- Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert:
Statistical fault injection: Quantified error and confidence.
502-506

- Hyun-jin Cho, Dongkun Shin, Young Ik Eom:
KAST: K-associative sector translation for NAND flash memory in real-time systems.
507-512

- Alexander Viehl, Michael Pressler, Oliver Bringmann, Wolfgang Rosenstiel:
White box performance analysis considering static non-preemptive software scheduling.
513-518

- Frank König, Dave Boers, Frank Slomka, Ulrich Margull, Michael Niemetz, Gerhard Wirrer:
Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems.
519-523

- Mircea Negrean, Simon Schliecker, Rolf Ernst:
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources.
524-529

- Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals:
Light NUCA: A proposal for bridging the inter-cache latency gap.
530-535

- Sotiria Fytraki, Dionisios N. Pnevmatikatos:
ReSim, a trace-driven, reconfigurable ILP processor simulator.
536-541

- Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration.
542-547

- Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels:
Algorithms for the automatic extension of an instruction-set.
548-553

- Bastian Ristau, Torsten Limberg, Oliver Arnold, Gerhard Fettweis:
Dimensioning heterogeneous MPSoCs via parallelism analysis.
554-557

- Leandro Fiorin, Gianluca Palermo, Cristina Silvano:
MPSoCs run-time monitoring through Networks-on-Chip.
558-561

- Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi:
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
562-565

- Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arjomand:
A hybrid packet-circuit switched on-chip network based on SDM.
566-569

- Lifeng Su, Stephan Courcambeck, Pierre Guillemin, Christian Schwarz, Renaud Pacalet:
SecBus: Operating System controlled hierarchical page-based memory bus protection.
570-573

- Jonas Diemer, Rolf Ernst:
A link arbitration scheme for quality of service in a latency-optimized network-on-chip.
574-577

- Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson:
Flow regulation for on-chip communication.
578-581

- Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Customizing IP cores for system-on-chip designs using extensive external don't-cares.
582-585

- Amin El Mrabti, Frédéric Pétrot, Aimen Bouchhima:
Extending IP-XACT to support an MDE based approach for SoC design.
586-589

- Christian Genz, Rolf Drechsler:
Overcoming limitations of the SystemC data introspection.
590-593

- Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage.
594-597

- Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete:
A power-efficient migration mechanism for D-NUCA caches.
598-601

- Yervant Zorian:
Panel Session - Vertical integration versus disaggregation.
602

- Pierre Garnier:
Trends and challenges in wireless application processors.
603

- Siddharth Garg, Diana Marculescu:
System-level process variability analysis and mitigation for 3D MPSoCs.
604-609

- Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad S. Bakir, Yogendra Joshi, Andrei Fedorov, Sung Kyu Lim:
Co-design of signal, power, and thermal distribution networks for 3D ICs.
610-615

- Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli:
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
616-621

- M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.
622-627

- Denis Réal, Frédéric Valette, M'hamed Drissi:
Enhancing correlation electromagnetic attack using planar near-field cartography.
628-633

- Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans:
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA.
634-639

- Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar:
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.
640-645

- Luca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner:
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT.
646-651

- Saugata Ghose, Latoya Gilgeous, Polina Dudnik, Aneesh Aggarwal, Corey Waxman:
Architectural support for low overhead detection of memory violations.
652-657

- Ilya Wagner, Valeria Bertacco:
Caspar: Hardware patching for multicore processors.
658-663

- Alessandro Cilardo:
A new speculative addition architecture suitable for two's complement operations.
664-669

- Pepijn J. de Langen, Ben H. H. Juurlink:
Limiting the number of dirty cache lines.
670-675

- Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol:
Contactless testing: Possibility or pipe-dream?
676-681

- Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng:
Analysis and optimization of fault-tolerant embedded systems with hardened processors.
682-687

- Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Jensen:
On bounding response times under software transactional memory in distributed multiprocessor real-time systems.
688-693

- Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo, Lothar Thiele:
An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems.
694-699

- Angan Das, Ranga Vemuri:
A graph grammar based approach to automated multi-objective analog circuit design.
700-705

- Pieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen:
Massively multi-topology sizing of analog integrated circuits.
706-711

- Sawal Ali, Li Ke, Reuben Wilcock, Peter R. Wilson:
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits.
712-717

- Dani Tannir, Roni Khazaka:
Computation of IP3 using single-tone moments analysis.
718-723

- Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang:
Formal approaches to analog circuit verification.
724-729

- Larry Toda, Walden C. Rhines:
Panel session - ESL methodology for SoC.
730

- Hai Li, Yiran Chen:
An overview of non-volatile memory technology and the implication for tools and architectures.
731-736

- Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie:
Power and performance of read-write aware Hybrid Caches with non-volatile memories.
737-742

- David Roberts, Taeho Kgil, Trevor N. Mudge:
Using non-volatile memory to save energy in servers.
743-748

- Nicola Concer, Salvatore Iamundo, Luciano Bononi:
aEqualized: A novel routing algorithm for the Spidergon Network On Chip.
749-754

- Zuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Jiaxin Li, Ning Deng, Licheng Xue, Yu-An Tan, Baojun Qiao:
Group-caching for NoC based multicore cache coherent systems.
755-760

- Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier:
A monitor interconnect and support subsystem for multicore processors.
761-766

- Giovanni Beltrame, Luca Fossati, Donatella Sciuto:
A real-time application design methodology for MPSoCs.
767-772

- Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk:
Adaptive prefetching for shared cache based chip multiprocessors.
773-778

- Krutartha Patel, Sri Parameswaran, Roshan G. Ragel:
CUFFS: An instruction count based architectural framework for security of MPSoCs.
779-784

- Daniel E. Holcomb, Wenchao Li, Sanjit A. Seshia:
Design as you see FIT: System-level soft error analysis of sequential circuits.
785-790

- Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Detecting errors using multi-cycle invariance information.
791-796

- Ping Lu, Daniel Glaser, Gürkan Uygur, Klaus Helmreich:
A novel approach to entirely integrate Virtual Test into test development flow.
797-802

- Michele Lombardi, Michela Milano, Luca Benini:
Robust non-preemptive hard real-time scheduling for clustered multicore platforms.
803-808

- Andrea Marongiu, Luca Benini:
Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy.
809-814

- Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan:
Using randomization to cope with circuit uncertainty.
815-820

- Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk:
Process variation aware thread mapping for Chip Multiprocessors.
821-826

- Stephan Held:
Gate sizing for large cell-based designs.
827-832

- Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani:
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
833-838

- Ye Tao, Sung Kyu Lim:
Decoupling capacitor planning with analytical delay model on RLC power grid.
839-844

- Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.
845-850

- Kai Richter, Marek Jersak, Rolf Ernst:
Learning early-stage platform dimensioning from late-stage timing verification.
851-857

- Stephan Reichelt, Oliver Scheickl, Gökhan Tabanoglu:
The influence of real-time constraints on the design of FlexRay-based systems.
858-863

- Alberto Ferrari, Marco Di Natale, Giacomo Gentile, Giovanni Reggiani, Paolo Gai:
Time and memory tradeoffs in the implementation of AUTOSAR components.
864-869

- Pankaj Bhagawat, Rajballav Dash, Gwan Choi:
Systolic like soft-detection architecture for 4×4 64-QAM MIMO system.
870-873

- Alain Fourmigue, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid:
Co-simulation based platform for wireless protocols design explorations.
874-877

- Elena Dubrova:
How to speed-up your NLFSR-based stream cipher.
878-881

- Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilker Hamzaoglu:
A high performance reconfigurable Motion Estimation hardware architecture.
882-885

- Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Partition-based exploration for reconfigurable JPEG designs.
886-889

- Sven van Haastregt, Bart Kienhuis:
Automated synthesis of streaming C applications to process networks in hardware.
890-893

- Federico Baronti, Francesco Lenzi, Roberto Roncella, Roberto Saletti:
Distributed sensor for steering wheel rip force measurement in driver fatigue detection.
894-897

- Saturnino Garcia, Alex Orailoglu:
Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy.
898-901

- Seongmoon Wang, Wenlong Wei:
Machine learning-based volume diagnosis.
902-905

- Francesco Paterna, Luca Benini, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Mauro Olivieri:
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip.
906-909

- Guido Schreiner, Endric Schubert:
Panel session - Architectures and integration for programmable SoC's.
910

- Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi:
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
911-916

- Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew:
Single ended 6T SRAM with isolated read-port for low-power embedded systems.
917-922

- Marco Facchini, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, Paul Marchal:
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
923-928

- Anselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini:
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
929-933

- Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna:
A case for multi-channel memories in video recording.
934-939

- Hajer Krichene Zrida, Abderrazek Jemai, Ahmed C. Ammari, Mohamed Abid:
High level H.264/AVC video encoder parallelization for multiprocessor implementation.
940-945

- Inchoon Yeo, Eun Jung Kim:
Temperature-aware scheduler based on thermal behavior grouping in multicore systems.
946-951

- Omer Khan, Sandip Kundu:
Hardware/software co-design architecture for thermal management of chip multiprocessors.
952-957

- Lars Bauer, Muhammad Shafique, Jörg Henkel:
Cross-architectural design space exploration tool for reconfigurable processors.
958-963

- Karel Bruneel, Fatma Abouelella, Dirk Stroobandt:
Automatically mapping applications to a self-reconfiguring platform.
964-969

- Andreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, Philipp A. Hartmann, Frank Oppenheimer:
OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems.
970-975

- Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann:
Design optimizations to improve placeability of partial reconfiguration modules.
976-981

- Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris:
Automated data analysis solutions to silicon debug.
982-987

- Aymen Ladhar, Mohamed Masmoudi, Laroussi Bouzaida:
Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data.
988-993

- Irith Pomeranz, Sudhakar M. Reddy:
Selection of a fault model for fault diagnosis based on unique responses.
994-999

- Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy:
Improving compressed test pattern generation for multiple scan chain failure diagnosis.
1000-1005

- Francesco Leonardi, Alessandro Pinto, Luca P. Carloni:
A case study in distributed deployment of embedded software for camera networks.
1006-1011

- Shou-Wei Chang, Kun-Yuan Hsieh, Jenq Kuen Lee:
pTest: An adaptive testing tool for concurrent software on embedded multicore processors.
1012-1017

- Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda:
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.
1018-1023

- Franco Fummi, Giovanni Perbellini, Niccolo Roncolato:
Networked embedded system applications design driven by an abstract middleware environment.
1024-1029

- Wolfgang Eberle, Ashwin S. Mecheri, Thi Kim Thoa Nguyen, Georges G. E. Gielen, Raymond Campagnolo, Alison Burdett, Chris Toumazou, Bart Volckaerts:
Health-care electronics The market, the challenges, the progress.
1030-1034

- Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyoshi, Ryuichiro Ohyama, Nobuhiro Nonogaki, Koji Kitayama, Tatsuya Mori, Yasuyuki Ueda, Hideho Arakida, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi, Nobu Matsumoto:
Design and implementation of scalable, transparent threads for multi-core media processor.
1035-1039

- Francois Kasperski, Olivier Pierrelee, Frederic Dotto, Michel Sarlotte:
High data rate fully flexible SDR modem advanced configurable architecture & development methodology.
1040-1044

- Pierre-Henri Bonnaud, Grit Sommer:
Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC.
1045-1050

- Ahmed Amine Jerraya, Gabriela Nicolescu:
Embedded tutorial - Understanding multicore technologies.
1051

- Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe Sun:
Latency criticality aware on-chip communication.
1052-1057

- Woo-Cheol Kwon, Sungjoo Yoo, Junhyung Um, Seh-Woong Jeong:
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem.
1058-1063

- Masoumeh Ebrahimi, Masoud Daneshtalab, Mohammad Hossein Neishaburi, Siamak Mohammadi, Ali Afzali-Kusha, Juha Plosila, Hannu Tenhunen:
An efficent dynamic multicast routing protocol for distributing traffic in NOCs.
1064-1069

- Mikael Millberg, Axel Jantsch:
Priority based forced requeue to reduce worst-case latencies for bursty traffic.
1070-1075

- Wenchao Li, Marco Di Natale, Wei Zheng, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia:
Optimizations of an application-level protocol for enhanced dependability in FlexRay.
1076-1081

- Eric Armengaud, Andreas Steininger:
Remote measurement of local oscillator drifts in FlexRay networks.
1082-1087

- Tobias Ziermann, Stefan Wildermann, Jürgen Teich:
CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates.
1088-1093

- Eleonora Marchetti, Luca Fanucci, Alessandro Rocchi, Marco De Marinis:
Shock immunity enhancement via resonance damping in gyroscopes for automotive applications.
1094-1099

- Natividad Martínez Madrid, Ralf Seepold, Alvaro Reina Nieves, J. Sáez Gomez, Alberto los Santos Aransay, P. Sanz Velasco, Carlos Rueda Morales, Felisa Ares:
Integration of an advanced emergency call subsystem into a car-gateway platform.
1100-1105

- Adam B. Kinsman, Nicola Nicolici:
Finite Precision bit-width allocation using SAT-Modulo Theory.
1106-1111

- Seungwhun Paik, Insup Shin, Youngsoo Shin:
HLS-l: High-level synthesis of high performance latch-based circuits.
1112-1117

- Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of streaming datapaths for arbitrary fixed permutations.
1118-1123

- Shahin Golshan, Eli Bozorgzadeh:
SEU-aware resource binding for modular redundancy based designs on FPGAs.
1124-1129

- Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Generation of compact test sets with high defect coverage.
1130-1135

- Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
A scalable method for the generation of small test sets.
1136-1141

- Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: An X-Fill method for quick-and-cool scan test.
1142-1147

- Rogier Baert, Erik Brockmeyer, Sven Wuytack, Thomas J. Ashby:
Exploring parallelizations of applications for MPSoC platforms using MPA.
1148-1153

- Silvia Mazzini, Stefano Puri, Tullio Vardanega:
An MDE methodology for the development of high-integrity real-time systems.
1154-1159

- Etienne Borde, Grégory Haïk, Laurent Pautet:
Mode-based reconfiguration of critical software component architectures.
1160-1165

- Zhibin Yang, Kai Hu, Dianfu Ma, Lei Pi:
Towards a formal semantics for the AADL behavior annex.
1166-1171

- Jorge Fernandez Villena, Gabriela Ciuprina, Daniel Ioan, Luis Miguel Silveira:
On the efficient reduction of complete EM based parametric models.
1172-1177

- Safar Hatami, Peter Feldmann, Soroush Abbaspour, Massoud Pedram:
Efficient compression and handling of current source model library waveforms.
1178-1183

- Quan Chen, Ngai Wong:
New simulation methodology of 3D surface roughness loss for interconnects modeling.
1184-1189

- Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles:
An efficient decoupling capacitance optimization using piecewise polynomial models.
1190-1195

- Jan-Hendrik Oetjens, Ralph Görgen, Joachim Gerlach, Wolfgang Nebel:
An automated flow for integrating hardware IP into the automotive systems engineering process.
1196-1201

- Steve Perry:
Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design.
1202-1207

- Patrice Joubert Doriol, Yamarita Villavicencio, Cristiano Forzan, Mario Rotigni, Giovanni Graziosi, Davide Pandini:
EMC-aware design on a microcontroller for automotive applications.
1208-1213

- Djones Lettnin, Pradeep Kumar Nalla, Jörg Behrend, Jürgen Ruf, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Volker Schönknecht, Stephan Reitemeyer:
Semiformal verification of temporal properties in automotive hardware dependent software.
1214-1217

- Jan Schat:
On the relationship between stuck-at fault coverage and transition fault coverage.
1218-1221

- Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme:
System-level hardware-based protection of memories against soft-errors.
1222-1225

- Francesco Abate, Luca Sterpone, Massimo Violante, Fernanda Lima Kastensmidt:
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
1226-1229

- David Novo, Min Li, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor:
Finite precision processing in wireless applications.
1230-1233

- Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang:
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test.
1234-1237

- Elie Maricau, Georges G. E. Gielen:
Efficient reliability simulation of analog ICs including variability and time-varying stress.
1238-1241

- Fabien Demangel, Nicolas Fau, Nicolas Drabik, François Charot, Christophe Wolinski:
A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications.
1242-1245

- Ulrich Kühne, Daniel Große, Rolf Drechsler:
Property analysis and design understanding.
1246-1249

- Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto:
Test exploration and validation using transaction level models.
1250-1253

- Peter Kollig, Colin Osborne, Tomas Henriksson:
Heterogeneous multi-core platform for consumer multimedia applications.
1254-1259

- C. H. van Berkel:
Multi-core for mobile phones.
1260-1265

- Eric Flamand:
Strategic directions towards multicore application specific computing.
1266

- Hengyu Long, Yongpan Liu, Xiaoguang Fan, Robert P. Dick, Huazhong Yang:
Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks.
1267-1272

- Varun Subramanian, Michael Gilberti, Alex Doboli:
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes.
1273-1278

- Yexin Zheng, Chao Huang:
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability.
1279-1283

- Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
Debugging of Toffoli networks.
1284-1289

- Yang Zhao, Krishnendu Chakrabarty:
Cross-contamination avoidance for droplet routing in digital microfluidic biochips.
1290-1295

- Daniel Schmidt, Matthias Berning, Norbert Wehn:
Error correction in single-hop wireless sensor networks - A case study.
1296-1301

- Xuan Guan, Hai Lin, Yunsi Fei:
Design of an application-specific instruction set processor for high-throughput and scalable FFT.
1302-1307

- Stefan Müller, Manuel Schreger, Marten Kabutz, Matthias Alles, Frank Kienle, Norbert Wehn:
A novel LDPC decoder for DVB-S2 IP.
1308-1313

- Andre Guntoro, Manfred Glesner:
A flexible floating-point wavelet transform and wavelet packet processor.
1314-1319

- Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On hierarchical statistical static timing analysis.
1320-1325

- André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the accuracy of SAT-based debugging.
1326-1331

- Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
GCS: High-performance gate-level simulation with GPGPUs.
1332-1337

- Xiao Liu, Qiang Xu:
Trace signal selection for visibility enhancement in post-silicon validation.
1338-1343

- Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A new design-for-test technique for SRAM core-cell stability faults.
1344-1348

- S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod:
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.
1349-1354

- Stefan Holst, Hans-Joachim Wunderlich:
A diagnosis algorithm for extreme space compaction.
1355-1360

- Ang-Chih Hsieh, TingTing Hwang:
Thermal-aware memory mapping in 3D designs.
1361-1366

- Jongeun Lee, Aviral Shrivastava:
Static analysis to mitigate soft errors in register files.
1367-1372

- Ozcan Ozturk, Mahmut T. Kandemir:
Using dynamic compilation for continuing execution under reduced memory availability.
1373-1378

- Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A design methodology for fully reconfigurable Delta-Sigma data converters.
1379-1384

- Peter R. Wilson, Reuben Wilcock:
Optimal sizing of configurable devices to reduce variability in integrated circuits.
1385-1390

- Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Dibin Zhu:
An automated design flow for vibration-based energy harvester systems.
1391-1396

- Chun Wei Lin, Bing-Shiun Hsieh, Yu Cheng Lin:
Enhanced design of filterless class-D audio amplifier.
1397-1402

- Ahmed Amine Jerraya, Rolf Ernst:
Panel session - Multicore, will Startups drive innovation?
1403

- Giacomo Paci, Davide Bertozzi, Luca Benini:
Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.
1404-1409

- Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici:
Dynamic thermal management in 3D multicore architectures.
1410-1415

- Foad Dabiri, Alireza Vahdatpour, Miodrag Potkonjak, Majid Sarrafzadeh:
Energy minimization for real-time systems with non-convex and discrete operation modes.
1416-1421

- Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung:
Exploiting narrow-width values for thermal-aware register file designs.
1422-1427

- Andrea Bartolini, Martino Ruggiero, Luca Benini:
Visual quality analysis for dynamic backlight scaling in LCD systems.
1428-1433

- Muhammad Shafique, Lars Bauer, Jörg Henkel:
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.
1434-1439

- Nabeel Iqbal, Jörg Henkel:
Efficient constant-time entropy decoding for H.264.
1440-1445

- Patrick Bellasi, William Fornaciari, David Siorpaes:
Predictive models for multimedia applications power consumption based on use-case and OS level analysis.
1446-1451

- Sivaram Gopalakrishnan, Priyank Kalla:
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis.
1452-1457

- Victor N. Kravets, Alan Mishchenko:
Sequential logic synthesis using symbolic bi-decomposition.
1458-1463

- Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
On decomposing Boolean functions via extended cofactoring.
1464-1469

- Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura:
Register placement for high-performance circuits.
1470-1475

- Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa:
Scalable Adaptive Scan (SAS).
1476-1481

- M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
LFSR-based test-data compression with self-stoppable seeds.
1482-1487

- Mahmut Yilmaz, Krishnendu Chakrabarty:
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects.
1488-1493

- Xiao Liu, Qiang Xu:
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment.
1494-1499

- Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Sara Vinco:
Correct-by-construction generation of device drivers based on RTL testbenches.
1500-1505

- Jun Zhu, Ingo Sander, Axel Jantsch:
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures.
1506-1511

- Subhankar Mukherjee, Antara Ain, S. K. Panda, Rajdeep Mukhopadhyay, Pallab Dasgupta:
A formal approach for specification-driven AMS behavioral model generation.
1512-1517

- Felix Madlener, H. Gregor Molter, Sorin A. Huss:
SC-DEVS: An efficient SystemC extension for the DEVS model of computation.
1518-1523

- Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan:
Exploiting clock skew scheduling for FPGA.
1524-1529

- Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.
1530-1535

- Huynh Phung Huynh, Tulika Mitra:
Runtime reconfiguration of custom instructions for real-time embedded systems.
1536-1541

- Ulf Schlichtmann, Manuel Schmidt, Harald Kinzelbach, Michael Pronath, Volker Glöckel, Manfred Dietrich, Uwe Eichler, Joachim Haase:
Digital design at a crossroads How to make statistical design methodologies industrially relevant.
1542-1547

- Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Performance optimal speed control of multi-core processors under thermal constraints.
1548-1551

- Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi, Jean-François Nezan:
Scalable compile-time scheduler for multi-core architectures.
1552-1555

- John Sartori, Rakesh Kumar:
Distributed peak power management for many-core architectures.
1556-1559

- Jens Braunes, Rainer G. Spallek:
Generating the trace qualification configuration for MCDS from a high level language.
1560-1563

- Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
1564-1567

- José C. Costa, José C. Monteiro:
A MILP-based approach to path sensitization of embedded software.
1568-1571

- Kristoffer Nyborg Gregertsen, Amund Skavhaug:
An efficient and deterministic multi-tasking run-time environment for Ada and the Ravenscar profile on the Atmel AVR®32 UC3 microcontroller.
1572-1575

- Mojtaba Sabeghi, Koen Bertels:
Toward a runtime system for reconfigurable computers: A virtualization approach.
1576-1579

- Eric Vecchié, Jean-Pierre Talpin, Klaus Schneider:
Separate compilation and execution of imperative synchronous modules.
1580-1583

- Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl:
Programming MPSoC platforms: Road works ahead!
1584-1589

- Benjamin Chambers, Panagiotis Manolios, Daron Vroon:
Faster SAT solving with better CNF generation.
1590-1595

- Florian Pigorsch, Christoph Scholl:
Exploiting structure in an AIG based QBF solver.
1596-1601

- Nannan He, Michael S. Hsiao:
An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification.
1602-1607

- Min Li, Robert Fasthuber, David Novo, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor:
Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.
1608-1613

- Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger:
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing.
1614-1619

- Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel:
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications.
1620-1625

- Josep Soler Garrido, Henning Vetter, Magnus Sandell, David Milford, Andy Lillie:
Implementation of a reduced-lattice MIMO detector for OFDM Systems.
1626-1631

- Henning Zabel, Wolfgang Müller:
Increased accuracy through noise injection in abstract RTOS simulation.
1632-1637

- Franco Fummi, Giovanni Perbellini, Davide Quaglia, Andrea Acquaviva:
Flexible energy-aware simulation of heterogenous wireless sensor networks.
1638-1643

- Ashish Darbari, Bashir M. Al-Hashimi, David Flynn, John Biggs:
Selective state retention design using symbolic simulation.
1644-1649

- Esa Korhonen, Juha Kostamovaara:
A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique.
1650-1655

- Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee:
A novel self-healing methodology for RF Amplifier circuits based on oscillation principles.
1656-1661

- Reik Muller, Carsten Wegener, Hans-Joachim Jentschel, Sebastian Sattler, Heinz Mattes:
An approach to linear model-based testing for nonlinear cascaded mixed-signal systems.
1662-1667

- Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris:
Enrichment of limited training sets in machine-learning-based analog/RF test.
1668-1673

- Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton:
Speculative reduction-based scalable redundancy identification.
1674-1679

- Jason Baumgartner, Hari Mony:
Scalable liveness checking via property-preserving transformations.
1680-1685

- Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marco Murciano, Sergio Nocco, Stefano Quer:
Speeding up model checking by exploiting explicit and hidden verification constraints.
1686-1691

- Mitra Purandare, Thomas Wahl, Daniel Kroening:
Strengthening properties using abstraction refinement.
1692-1697

- Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith:
Sequential logic rectifications with approximate SPFDs.
1698-1703

- David Bañeres, Jordi Cortadella, Michael Kishinevsky:
Variable-latency design by function speculation.
1704-1709

- Vijay D'Silva, Daniel Kroening:
Fixed points for multi-cycle path detection.
1710-1715

Last update Sat May 18 18:22:05 2013
CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page