DATE 2011: Grenoble, France

Keynote

• Stephen B. Furber:
  Biologically-inspired massively-parallel architectures - Computing beyond a million processors. 1
  

System-Level Techniques to Handle Performance, Reliability and Thermal Issues

• Vivek J. Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
  VESPA: Variability emulation for System-on-Chip performance analysis. 2-7
  
• Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang:
  Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. 8-13
  
• Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao:
  An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems. 14-19
  
• Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li:
  Register allocation for simultaneous reduction of energy and peak temperature on registers. 20-25
  

Modeling and Simulation of Interconnects

• L. Gobbato, Alessandro Chinea, Stefano Grivet-Talocia:
  A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels. 26-31
  
• Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luis Miguel Silveira, Nick van der Meijs:
  Fast statistical analysis of RC nets subject to manufacturing variabilities. 31-37
  
• Baktash Boghrati, Sachin S. Sapatnekar:
  A scaled random walk solver for fast power grid analysis. 38-43
  
• Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong:
  A block-diagonal structured model reduction scheme for power grid networks. 44-49
  

Logic Synthesis and Place and Route: After 20 Years of Engagement, Wedding in View? (Panel/Tutorial)

• Giovanni De Micheli:
  Logic synthesis and physical design: Quo vadis? 50
  
• Marco Casale-Rossi, Antun Domic:
  Panel and embedded tutorial - Logic synthesis and place and route: After 20 years of engagement, wedding in view? 51
  

Transient Faults and Soft Errors

• David J. Palframan, Nam Sung Kim, Mikko H. Lipasti:
  Time redundant parity for low-cost transient error detection. 52-57
  
• Keheng Huang, Yu Hu, Xiaowei Li:
  Cross-layer optimized placement and routing for FPGA soft error mitigation. 58-63
  
• Chien-Chih Yu, John P. Hayes:
  Trigonometric method to handle realistic error probabilities in logic circuits. 64-69
  
• Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori:
  Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). 70-75
  

Networked Embedded Systems

• Martin Lukasiewycz, Samarjit Chakraborty, Paul Milbredt:
  FlexRay switch scheduling - A networking concept for electric vehicles. 76-81
  
• Kay Klobedanz, Andreas Koenig, Wolfgang Müller:
  A reconfiguration approach for fault-tolerant FlexRay networks. 82-87
  
• Lan S. Bai, Robert P. Dick, Peter A. Dinda, Pai H. Chou:
  Simplified programming of faulty sensor networks via code transformation and run-time interval computation. 88-93
  

Design of Energy-Efficient and Automotive Systems

• Nafsika Chrysanthou, Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou:
  Parallel accelerators for GlimmerHMM bioinformatics algorithm. 94-99
  
• Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini:
  An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms. 100-105
  
• Jatin N. Mistry, Bashir M. Al-Hashimi, David Flynn, Stephen Hill:
  Sub-clock power-gating technique for minimising leakage power during active mode. 106-111
  
• Andreas Kern, Thilo Streichert, Jürgen Teich:
  An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). 112-117
  
• Sebastian Siegl, Kai-Steffen Jens Hielscher, Reinhard German, Christian Berger:
  Formal specification and systematic model-driven testing of embedded automotive systems. 118-123
  

Embedded Tutorial

• Bhanu Kapoor, Knut M. Just:
  Embedded tutorial: Addressing critical power management verification issues in low power designs. 124
  

Power Optimization of Multi-Core Architectures

• Koushik Chakraborty, Sanghamitra Roy:
  Topologically homogeneous power-performance heterogeneous multicore systems. 125-130
  
• Lucas Francisco Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava:
  Variability-aware duty cycle scheduling in long running embedded sensing systems. 131-136
  
• Vinay Hanumaiah, Sarma B. K. Vrudhula:
  Reliability-aware thermal management for hard real-time applications on multi-core processors. 137-142
  

Core Algorithms for Formal Verification Engines

• HyoJung Han, HoonSang Jin, Fabio Somenzi:
  Clause simplification through dominator analysis. 143-148
  
• Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker:
  Integration of orthogonal QBF solving techniques. 149-154
  
• Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel:
  STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra. 155-160
  

Predicting Bugs and Generating Tests for Validation

• Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Yue Wu, Weiwu Hu:
  Empirical design bugs prediction for verification. 161-166
  
• Mingsong Chen, Prabhat Mishra:
  Decision ordering based property decomposition for functional test generation. 167-172
  
• Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan:
  Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. 173-178
  
• Jörg Behrend, Djones Lettnin, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel:
  Scalable hybrid verification for embedded software. 179-184
  

Timing Related Issues in Test

• Mingjing Chen, Alex Orailoglu:
  Diagnosing scan chain timing faults through statistical feature analysis of scan images. 185-190
  
• Mainak Banga, Nikhil P. Rahagude, Michael S. Hsiao:
  Design-for-test methodology for non-scan at-speed testing. 191-196
  
• Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu:
  A clock-gating based capture power droop reduction methodology for at-speed scan testing. 197-203
  

Performance and Timing Analysis

• Sidharta Andalam, Partha S. Roop, Alain Girault:
  Pruning infeasible paths for tight WCRT analysis of synchronous programs. 204-209
  
• Stefan Stattelmann, Oliver Bringmann, Wolfgang Rosenstiel:
  Fast and accurate resource conflict simulation for performance analysis of multi-core systems. 210-215
  
• Zhonglei Wang, Kun Lu, Andreas Herkersdorf:
  An approach to improve accuracy of source-level TLMs of embedded software. 216-221
  
• Parisa Razaghi, Andreas Gerstlauer:
  Host-compiled multicore RTOS simulator for embedded real-time software development. 222-227
  

Implementations for Digital Baseband Processing

• Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
  A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. 228-233
  
• Christian Bernard, Fabien Clermidy:
  A low-power VLIW processor for 3GPP-LTE complex numbers processing. 234-239
  
• Nils Heidmann, Till Wiegand, Steffen Paul:
  Architecture and FPGA-implementation of a high throughput K⁺-Best detector. 240-245
  
• Nariman Moezzi Madani, Thorlindur Thorolfsson, Joseph Crop, Patrick Chiang, W. Rhett Davis:
  An energy-efficient 64-QAM MIMO detector for emerging wireless standards. 246-251
  

Panel

• Barry M. Pangrle, John Biggs, C. Clavel, Olivier Domerego, Knut M. Just:
  Beyond UPF & CPF: Low-power design and verification. 252
  

Interactive Presentations

• Mohammed G. Khatib, Leon Abelmann:
  Buffering implications for the design space of streaming MEMS storage. 253-256
  
• Ankit Goyal, Farid N. Najm:
  Efficient RC power grid verification using node elimination. 257-260
  
• Michael B. Healy, Sung Kyu Lim:
  A novel TSV topology for many-tier 3D power-delivery networks. 261-264
  
• Nor Zaidi Haron, Said Hamdioui:
  Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories. 265-268
  
• Tobias Ziermann, Jürgen Teich, Zoran Salcic:
  DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. 269-272
  
• Simone Sabatelli, Francesco Sechi, Luca Fanucci, Alessandro Rocchi:
  A sensor fusion algorithm for an integrated angular position estimation with inertial measurement units. 273-276
  
• Luc Michel, Nicolas Fournel, Frédéric Pétrot:
  Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation. 277-280
  
• Linwei Niu:
  System-level energy-efficient scheduling for hard real-time embedded systems. 281-284
  
• Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag:
  Timing error statistics for energy-efficient robust DSP systems. 285-288
  
• Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi:
  ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications. 298-292
  

Robust and Low Power Systems

• T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar:
  Enabling improved power management in multicore processors through clustered DVFS. 293-298
  
• Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel:
  Dynamic thermal management in 3D multi-core architecture through run-time adaptation. 299-304
  
• Ilya Wagner, Shih-Lien Lu:
  Distributed hardware matcher framework for SoC survivability. 305-310
  
• Songjun Pan, Yu Hu, Xing Hu, Xiaowei Li:
  A cost-effective substantial-impact-filter based method to tolerate voltage emergencies. 311-315
  

Formal Verification Techniques and Applications

• Gianpiero Cabodi, Sergio Nocco, Stefano Quer:
  Interpolation sequences revisited. 316-322
  
• Brian Keng, Sean Safarpour, Andreas G. Veneris:
  Automated debugging of SystemVerilog assertions. 323-328
  
• Bryan A. Brady, Daniel E. Holcomb, Sanjit A. Seshia:
  Counterexample-guided SMT-driven optimal buffer sizing. 329-334
  

System Level Simulation and Validation

• Peng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay:
  DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. 335-340
  
• Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay:
  Cycle-count-accurate processor modeling for fast and accurate system-level simulation. 341-346
  
• Cheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay:
  A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. 347-352
  
• Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin:
  Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. 353-358
  

Advances in Analogue, Mixed Signal and RF Testing

• Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng:
  An all-digital built-in self-test technique for transfer function characterization of RF PLLs. 359-364
  
• Pedro Fonseca da Mota, José Machado da Silva:
  A true power detector for RF PA built-in calibration and testing. 365-370
  
• Hamidreza Hashempour, Jos Dohmen, Bratislav Tasic, Bram Kruseman, Camelia Hora, Maikel van Beurden, Yizi Xing:
  Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example. 371-376
  
• Mohit Singh, Mahendra Sakare, Shalabh Gupta:
  Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". 377-382
  

Design Automation Methodologies and Architectures for Three-Dimensional ICs

• Da-Cheng Juan, Siddharth Garg, Diana Marculescu:
  Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations. 383-388
  
• Christian Weis, Norbert Wehn, Igor Loi, Luca Benini:
  Design space exploration for 3D-stacked DRAMs. 389-394
  
• Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli:
  Analytical heat transfer model for thermal through-silicon vias. 395-400
  
• Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang:
  A new architecture for power network in 3D IC. 401-406
  

Resource Management for QoS Guaranteed NoCs

• Everton Carara, Gabriel Marchesan Almeida, Gilles Sassatelli, Fernando Gehm Moraes:
  Achieving composability in NoC-based MPSoCs through QoS management at software level. 407-412
  
• Marjan Asadinia, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad:
  Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links. 413-418
  
• Markus Winter, Gerhard Fettweis:
  Guaranteed service virtual channel allocation in NoCs for run-time task scheduling. 419-424
  
• A. Beyranvand Nejad, M. Escudero Martinez, Kees Goossens:
  An FPGA bridge preserving traffic quality of service for on-chip network-based systems. 425-430
  

Smart Devices Embedded Tutorial - Smart Devices for the Cloud Era

• Gerhard Fettweis, Falko Guderian, Stefan Krone:
  Entering the path towards terabit/s wireless links. 431-436
  
• Antoine Dupret, Michaël Tchagaspanian, Arnaud Verdant, Laurent Alacoque, Arnaud Peizerat:
  Smart imagers of the future. 437-442
  

An Encyclopedia of Routing

• Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth:
  Power-driven global routing for multi-supply voltage domains. 443-448
  
• Jin-Tai Yan, Zhi-Wei Chen:
  Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. 449-454
  
• Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin:
  Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. 455-460
  
• Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani:
  On routing fixed escaped boundary pins for high speed boards. 461-466
  

Temperature and Variation Aware Design in Low Power Systems

• Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun:
  Dynamic write limited minimum operating voltage for nanoscale SRAMs. 467-472
  
• Mohammad Ghasemazar, Massoud Pedram:
  Variation aware dynamic power management for chip multiprocessor architectures. 473-478
  
• Huang Huang, Gang Quan:
  Leakage aware energy minimization for real-time systems under the maximum temperature constraint. 479-484
  

Advanced NoC Tooling and Architectures

• Anita Tino, Gul N. Khan:
  Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures. 485-490
  
• Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini:
  A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. 491-496
  
• Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi:
  Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. 497-502
  

Industrial 1

• A. Matsuda, T. Ishihara:
  Developing an integrated verification and debug methodology. 503-504
  
• Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas:
  An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. 505-506
  
• B. Kapoor, A. Hunter, P. Tiwari:
  Power management verification experiences in Wireless SoCs. 507-508
  
• Tsunwai Gary Yip, Philip Yeung, Ming Li, Deborah Dressler:
  Challenges in designing high speed memory subsystem for mobile applications. 509-510
  
• M. Mazzillo, P. G. Fallica, E. Ficarra, A. Messina, M. Romeo, Roberto Zafalon:
  Solid state photodetectors for nuclear medical imaging applications. 511-512
  
• Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Oscar Ballan:
  Fault grading of software-based self-test procedures for dependable automotive applications. 513-514
  

Analysis, Compilation and Runtime Techniques

• Janmartin Jahn, Mohammad Abdullah Al Faruque, Jörg Henkel:
  CARAT: Context-aware runtime adaptive task migration for multi core architectures. 515-520
  
• Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich:
  A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. 521-526
  
• José Baiocchi, Bruce R. Childers:
  Demand code paging for NAND flash in MMU-less embedded systems. 517-532
  

Embedded Tutorial

• Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera:
  Architectures for online error detection and recovery in multicore processors. 533-538
  

Interactive Presentations

• Jishen Zhao, Xiangyu Dong, Yuan Xie:
  An energy-efficient 3D CMP design with fine-grained voltage scaling. 539-542
  
• Gianpiero Cabodi, Sergio Nocco:
  Optimized model checking of multiple properties. 543-546
  
• Dusung Kim, Maciej J. Ciesielski, Seiyang Yang:
  A new distributed event-driven gate-level HDL simulation by accurate prediction. 547-550
  
• Lakshmanan Balasubramanian, Puneet Sabbarwal, R. K. Mittal, Prakash Narayanan, R. K. Dash, A. D. Kudari, S. Manian, S. Polarouthu, Harikrishna Parthasarathy, R. C. Vijayaraghavan, S. Turkewadikar:
  Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. 551-554
  
• Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
  A 3D reconfigurable platform for 4G telecom applications. 555-558
  
• S. Kobayashi, K. Horiuchi:
  An LOCV-based static timing analysis considering spatial correlations of power supply variations. 559-562
  
• Claus Traulsen, T. Amende, Reinhard von Hanxleden:
  Compiling SyncCharts to Synchronous C. 563-566
  
• Xiaotao Chang, Yike Ma, Hubertus Franke, Kun Wang, Rui Hou, Hao Yu, Terry Nelms:
  Optimization of stateful hardware acceleration in hybrid architectures. 567-570
  
• Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo:
  Formal reset recovery slack calculation at the register transfer level. 571-574
  
• Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu, El Mostapha Aboulhamid, Ian O'Connor:
  Multi-granularity thermal evaluation of 3D MPSoC architectures. 575-578
  
• David C. Keezer, Carl Edward Gray:
  Two methods for 24 Gbps test signal synthesis. 579-582
  
• Yi-Chung Chen, Hai Li, Yiran Chen, Robinson E. Pino:
  3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. 583-586
  
• Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang:
  Architectural exploration of 3D FPGAs towards a better balance between area and delay. 587-590
  
• Joel Porquet, Alain Greiner, Christian Schwarz:
  NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs. 591-594
  

Embedded Tutorial

• Attila Bilgic, Vincent Pichot, Michael Gerding, Felix Bruns:
  Low-power smart industrial control. 595-599
  
• Mark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Danny Kershaw, Dennis Sylvester, David Blaauw, Trevor N. Mudge:
  Low power interconnects for SIMD computers. 600-605
  

Keynote

• Hannu Kauppinen:
  Wireless innovations for smartphones. 606
  

Placement and Floorplanning

• Markus Struzyna:
  Flow-based partitioning and position constraints in VLSI placement. 607-612
  
• Yuankai Chen, Hai Zhou, Robert P. Dick:
  Integrated circuit white space redistribution for temperature optimization. 613-618
  
• Zhi-Wei Chen, Jin-Tai Yan:
  Timing-constrained I/O buffer placement for flip-chip designs. 619-624
  
• Licheng Xue, Weixing Ji, Qi Zuo, Yang Zhang:
  Floorplanning exploration and performance evaluation of a new Network-on-Chip. 625-630
  

Power Modeling, Analysis and Optimization

• Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele:
  Worst-case temperature analysis for real-time systems. 631-636
  
• Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen:
  Black-box leakage power modeling for cell library and SRAM compiler. 637-642
  
• Shih-Jung Hsu, Rung-Bin Lin:
  Clock gating optimization with delay-matching. 643-648
  
• Pallavi Reddy, Fabien Clermidy, Amer Baghdadi, Michel Jézéquel:
  A low complexity stopping criterion for reducing power consumption in turbo decoders. 649-654
  
• Hyunsun Park, Sungjoo Yoo, Sunggu Lee:
  A novel tag access scheme for low power L2 cache. 655-660
  

Design and Test of Fault Resilient NoC Architectures

• Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi:
  Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. 661-666
  
• Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
  ReliNoC: A reliable network for priority-based on-chip communication. 667-672
  
• Chen-Ling Chou, Radu Marculescu:
  FARM: Fault-aware resource management in NoC-based multiprocessor platforms. 673-678
  

New Techniques for Diagnosis and Debug

• Jing Ye, Yu Hu, Xiaowei Li:
  On diagnosis of multiple faults using compacted responses. 679-684
  
• Xiao Liu, Qiang Xu:
  On multiplexed signal tracing for post-silicon debug. 685-690
  
• Jianliang Gao, Yinhe Han, Xiaowei Li:
  Eliminating data invalidation in debugging multiple-clock chips. 691-696
  

Embedded Software for Parallel Architectures

• Stefan J. Geuns, Marco Jan Gerrit Bekooij, Tjerk Bijlsma, Henk Corporaal:
  Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems. 697-702
  
• Tianji Wu, Di Wu, Yu Wang, Xiaorui Zhang, Hong Luo, Ningyi Xu, Huazhong Yang:
  Gemma in April: A matrix-like parallel programming architecture on OpenCL. 703-708
  
• Shuai Mu, Chenxi Wang, Ming Liu, Dongdong Li, Maohua Zhu, Xiaoliang Chen, Xiang Xie, Yangdong Deng:
  Evaluating the potential of graphics processors for high performance embedded computing. 709-714
  

Virtual Manycore Platforms: Moving Towards 100+ Processor Cores

• Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen:
  Virtual Manycore platforms: Moving towards 100+ processor cores. 715-720
  

Panel

• Markus Winterholer:
  Embedded software debug and test: Needs and requirements for innovations in debugging. 721
  

Smart Medical Implants

• Jan M. Rabaey, Michael Mark, David Chen, Christopher Sutardja, Chongxuan Tang, Suraj Gowda, Mark Wagner, Dan Werthimer:
  Powering and communicating with mm-size implants. 722-727
  
• Emeric de Foucauld, Jean-Baptiste David, Christophe Delaveaud, Pascal Ciais:
  An antenna-filter codesign for cardiac implants. 728-733
  

Emerging Memory Technologies

• Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
  Design implications of memristor-based RRAM cross-point structures. 734-739
  
• Xuebei Yang, Kartik Mohanram:
  Robust 6T Si tunneling transistor SRAM design. 740-745
  
• Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha:
  Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory. 746-751
  

Architectural Optimization for Low Power Systems

• Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar:
  A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. 752-757
  
• Ku He, Andreas Gerstlauer, Michael Orshansky:
  Controlled timing-error acceptance for low energy IDCT design. 758-763
  
• Lingamneni Avinash, Christian C. Enz, Jean-Luc Nagel, Krishna V. Palem, Christian Piguet:
  Energy parsimonious circuit design through probabilistic pruning. 764-769
  
• Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
  Stage number optimization for switched capacitor power converters in micro-scale energy harvesting. 770-775
  

Advanced Technologies for NoC Implementation

• Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
  Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. 776-781
  
• Gilbert Hendry, Johnnie Chan, Luca P. Carloni, Keren Bergman:
  VANDAL: A tool for the design specification of nanophotonic networks. 782-787
  
• Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
  Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. 788-793
  

Emerging Test Solutions for Advanced Technologies, RF and MEMS Devices

• Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir:
  Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. 794-799
  
• Aswin Sreedhar, Sandip Kundu:
  On design of test structures for lithographic process corner identification. 800-805
  
• Ahmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly, Pascal Nouet:
  An electrical test method for MEMS convective accelerometers: Development and evaluation. 806-811
  
• Nathan Kupp, Mustapha Slamani, Yiorgos Makris:
  Correlating inline data with final test outcomes in analog/RF devices. 812-817
  

Innovative Power-Aware Systems for a Green and Healthy Society

• Carolina Mora Lopez, Silke Musa, Carmen Bartic, Robert Puers, Georges G. E. Gielen, Wolfgang Eberle:
  Systematic design of a programmable low-noise CMOS neural interface for cell activity recording. 818-823
  
• Karim Kanoun, Hossein Mamaghanian, Nadia Khaled, David Atienza:
  A real-time compressed sensing-based personal electrocardiogram monitoring system. 824-829
  
• Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini:
  A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores. 830-835
  
• Davide Carli, Davide Brunelli, Luca Benini, Massimiliano Ruggeri:
  An effective multi-source energy harvester for low power applications. 836-841
  

Foundations of Component-Based Design for Embedded Systems

• Simon Perathoner, Kai Lampka, Lothar Thiele:
  Composing heterogeneous components for system-wide performance analysis. 842-847
  

Embedded Tutorial

• Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera:
  Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. 848-850
  
• Benny Akesson, Kees Goossens:
  Architectures and modeling of predictable memory controllers for improved system integration. 851-856
  
• Pieter van der Wolf, Jeroen Geuzebroek:
  SoC infrastructures for predictable system integration. 857-862
  

Interactive Presentations

• Jeonghee Shin, John A. Darringer, Guojie Luo, Alan J. Weger, C. L. Johnson:
  Early chip planning cockpit. 863-866
  
• Mohammad Rahman, Hiran Tennakoon, Carl Sechen:
  Power reduction via near-optimal library-based cell-size selection. 867-870
  
• Kang Kang, Y. S. Deng:
  Scalable packet classification via GPU metaprogramming. 871-874
  
• Donghwa Shin, Younghyun Kim, Jaeam Seo, Naehyuck Chang, Yanzhi Wang, Massoud Pedram:
  Battery-supercapacitor hybrid system for high-rate pulsed load applications. 875-878
  
• Salvatore Pontarelli, Marco Ottavi, Adelio Salsano, Kamran Zarrineh:
  Feedback based droop mitigation. 879-882
  
• Peng Qiao, Henk Corporaal, Menno Lindwer:
  A 0.964mW digital hearing aid system. 883-886
  
• Azalia Mirhoseini, Farinaz Koushanfar:
  HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiency. 887-890
  
• Pranav Tendulkar, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Dimitrios S. Nikolopoulos, Manolis Katevenis:
  Fine-grain OpenMP runtime support with explicit communication hardware primitives. 891-894
  
• Kohei Miyase, X. Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
  Transition-Time-Relation based capture-safety checking for at-speed scan test generation. 895-898
  
• Clinton K. Landrock, Badr Omrane, Yindar Chuo, Bozena Kaminska, Jeydmer Aristizabal:
  2D and 3D integration with organic and silicon electronics. 899-904
  
• Alex S. Weddell, Geoff V. Merrett, Bashir M. Al-Hashimi:
  Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes. 905-908
  
• Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis:
  A fault-tolerant deadlock-free adaptive routing for on chip interconnects. 909-912
  

Panel

• Ahmed Jerraya, John Goodacre:
  Smart devices panel session - Integrating the real world interfaces. 913
  

System-Level Design Techniques for Automotive Systems

• Dip Goswami, Reinhard Schneider, Samarjit Chakraborty:
  Re-engineering cyber-physical control applications for hybrid communication protocols. 914-919
  
• Pascal Montag, Sebastian Altmeyer:
  Precise WCET calculation in highly variant real-time systems. 920-925
  
• Thijs Schenkelaars, Bart Vermeulen, Kees Goossens:
  Optimal scheduling of switched FlexRay networks. 926-931
  

Power/Error Tradeoffs

• Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar:
  On the efficacy of NBTI mitigation techniques. 932-937
  
• Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
  Partitioned cache architectures for reduced NBTI-induced aging. 938-943
  
• Philipp Klaus Krause, Ilia Polian:
  Adaptive voltage over-scaling for resilient applications. 944-949
  
• Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy:
  Design of voltage-scalable meta-functions for approximate computing. 950-955
  

Memory System Architectures

• S. Phadke, S. Narayanasamy:
  MLP aware heterogeneous memory system. 956-961
  
• Alexandre Peixoto Ferreira, Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé:
  Impact of process variation on endurance algorithms for wear-prone memories. 962-967
  
• Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
  Flex memory: Exploiting and managing abundant off-chip optical bandwidth. 968-973
  
• Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
  Scratchpad memory optimizations for digital signal processing applications. 974-979
  

Testing and Designing SRAM Memories

• Elena I. Vatajelu, Joan Figueras:
  Robustness analysis of 6T SRAMs in memory retention mode under PVT variations. 980-985
  
• Bartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura:
  Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. 986-991
  
• Lin Li, Youtao Zhang, Jun Yang:
  Proactive recovery for BTI in high-k SRAM cells. 992-997
  

Cryptanalysis, Attacks and Countermeasures

• Alessandro Cilardo:
  The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1. 998-1003
  
• Olivier Meynard, Denis Réal, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger:
  Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques. 1004-1009
  
• Kun Ma, Kaijie Wu:
  LOEDAR: A low cost error detection and recovery scheme for ECC. 1010-1015
  
• Dusko Karaklajic, Junfeng Fan, Jörn-Marc Schmidt, Ingrid Verbauwhede:
  Low-cost fault detection method for ECC using Montgomery powering ladder. 1016-1021
  

Flows, Application and Future of Component-based Design for Embedded Systems

• Joseph Sifakis:
  Methods and tools for component-based system design. 1022
  
• Werner Damm, Hardi Hungar, Bernhard Josko, Thomas Peikenkamp, Ingo Stierand:
  Using contract-based component specifications for virtual integration testing and architecture design. 1023-1028
  
• Edward A. Lee, Alberto L. Sangiovanni-Vincentelli:
  Component-based design for the future. 1029
  

Embedded Tutorial - Communication Networks in Next Generation Automobiles

• Leandro D'Orazio, Filippo Visintainer, Marco Darin:
  Sensor networks on the car: State of the art and future challenges. 1030-1035
  
• Rainer Matischek, Thomas Herndl, Christoph Grimm, Jan Haase:
  Real-time wireless communication in automotive applications. 1036-1041
  
• Stefan Mahlknecht, Tom J. Kazmierski, Christoph Grimm, Leran Wang:
  Wireless communication and energy harvesting in automobiles. 1042-1047
  

Intelligent Energy Management Tutorial - Energy Transfer, Generation and Power Electronics

• Jess Brown:
  Power management trends in portable consumer applications. 1048-1052
  

Design Automation Methodologies for Emerging Technologies

• F. Liu, Xiaokang Shi:
  An efficient mask optimization method based on homotopy continuation technique. 1053-1058
  
• Sudip Roy, Bhargab B. Bhattacharya, Krishnendu Chakrabarty:
  Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips. 1059-1064
  
• Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, Swarup Bhunia:
  High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches. 1065-1070
  
• Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta:
  Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface. 1071-1076
  

System Modeling

• Mathias Soeken, Robert Wille, Rolf Drechsler:
  Verifying dynamic aspects of UML models. 1077-1082
  
• Lan S. Bai, Robert P. Dick, Pai H. Chou, Peter A. Dinda:
  Automated construction of fast and accurate system-level models for wireless sensor networks. 1083-1088
  
• Leandro Soares Indrusiak, Osmar Marchi dos Santos:
  Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration. 1089-1094
  
• Andrew Cassidy, Kai Yu, Haolang Zhou, Andreas G. Andreou:
  A high-level analytical model for application specific CMP design exploration. 1095-1100
  

Modeling and Verification of Analogue and RF Circuits

• Bo Liu, Ying He, Patrick Reynaert, Georges G. E. Gielen:
  Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model. 1101-1106
  
• Stefan Erb, Wolfgang Pribyl:
  A method for fast jitter tolerance analysis of high-speed PLLs. 1107-1112
  
• Karthik V. Aadithya, Alper Demir, Sriramkumar Venugopalan, Jaijeet S. Roychowdhury:
  SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs. 1113-1118
  

Industrial 2

• Giuseppe Pasetti, Nico Costantino, Francesco Tinfena, Riccardo Serventi, Paolo D'Abramo, Sergio Saponara, Luca Fanucci:
  Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects. 1119-1120
  
• Alberto Bonanno, Alberto Bocca, Marco Sabatini:
  Energy analysis methods and tools for modelling and Optimizing monitoring tyre systems. 1121-1122
  
• Andrea Acquaviva, Massimo Poncino, Marco Otella, Michele Sciolla:
  System level techniques to improve reliability in high power microcontrollers for automotive applications. 1123-1124
  
• Miltos D. Grammatikakis, Stratos Politis, Jean-Pierre Schoellkopf, Constantin Papadas:
  System-level power estimation methodology using cycle- and bit-accurate TLM. 1125-1126
  
• Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino:
  Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. 1127-1128
  

Embedded System Resource Allocation and Management

• Jia Huang, Andreas Raabe, Christian Buckl, Alois Knoll:
  A workflow for runtime adaptive task allocation on heterogeneous MPSoCs. 1119-1134
  
• Fanxin Kong, Wang Yi, Qingxu Deng:
  Energy-efficient scheduling of real-time tasks on cluster-based multicores. 1135-1140
  
• Luis Angel D. Bathen, Nikil D. Dutt:
  E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories. 1141-1146
  

Embedded Tutorial - Sub-Wave Length Lithography and Variability Aware Test and Characterization Methods

• Sandip Kundu, Aswin Sreedhar:
  Modeling manufacturing process variation for design and test. 1147-1152
  
• Miguel Miranda, Paul Zuber, Petr Dobrovolný, Philippe Roussel:
  Variability aware modeling for yield enhancement of SRAM and logic. 1153-1158
  
• R. Aitken, Greg Yeric, D. Flynn:
  Correlating models and silicon for improved parametric yield. 1159-1163
  

Interactive Presentations

• Alexandre M. Amory, Luciano Ost, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski:
  Evaluating energy consumption of homogeneous MPSoCs using spare tiles. 1164-1167
  
• Leonardo Kunz, Gustavo Girão, F. R. Wagner:
  Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC. 1168-1171
  
• Vikas Chandra, Robert C. Aitken:
  Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown. 1172-1175
  
• Subidh Ali, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Swarup Bhunia:
  Multi-level attacks: An emerging security concern for cryptographic hardware. 1176-1179
  
• Himanshu Thapliyal, N. Ranganathan:
  A new reversible design of BCD adder. 1180-1183
  
• Giovanni Funchal, Matthieu Moy:
  jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip. 1184-1187
  
• Rajeev Narayanan, Mohamed H. Zaki, Sofiène Tahar:
  Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching. 1188-1191
  
• Giovanni Beltrame, Gabriela Nicolescu:
  A multi-objective decision-theoretic exploration algorithm for platform-based design. 1192-1195
  
• Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
  Predicting bus contention effects on energy and performance in multi-processor SoCs. 1196-1199
  
• Libo Huang, Zhiying Wang, Li Shen, Hongyi Lu, Nong Xiao, Cong Liu:
  A specialized low-cost vectorized loop buffer for embedded processors. 1200-1203
  
• Robert Wille, Oliver Keszocze, Rolf Drechsler:
  Determining the minimal number of lines for large reversible circuits. 1204-1207
  
• Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Jean-Philippe Diguet, Sébastien Guillet:
  Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation. 1208-1211
  
• Cristian Ferent, Alex Doboli:
  A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features. 1212-1217
  
• Guibin Wang:
  Coordinate strip-mining and kernel fusion to lower power consumption on GPU. 1218-1219
  
• Francesco Bruschi, Francesco Perini, Vincenzo Rana, Donatella Sciuto:
  An efficient Quantum-Dot Cellular Automata adder. 1220-1223
  

Smart Energy Generation: Design Automation and the Smart-Grid

• Yuvraj Agarwal, Thomas Weng, Rajesh K. Gupta:
  Understanding the role of buildings in a smart microgrid. 1224-1229
  

Keynote

• Carmelo Papa:
  Smart systems at ST. 1230
  

Advanced Algorithms and Applications for Reconfigurable Computing

• Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
  Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs. 1231-1236
  
• Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan:
  SHARC: A streaming model for FPGA accelerators and its application to Saliency. 1237-1242
  
• Mona Safar, M. Watheq El-Kharashi, Mohamed Shalan, Ashraf Salem:
  A reconfigurable, pipelined, conflict directed jumping search SAT solver. 1243-1248
  

System Optimizations and Adaptivity

• Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John Lach, Kevin Skadron:
  Reducing the cost of redundant execution in safety-critical systems using relaxed dedication. 1249-1254
  
• Chengmo Yang, Alex Orailoglu:
  Frugal but flexible multicore topologies in support of resource variation-driven adaptivity. 1255-1260
  
• Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jörg Henkel:
  Minority-Game-based resource allocation for run-time reconfigurable multi-core processors. 1261-1266
  

Design and Simulation of Mixed-Signal Systems

• Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Alex S. Weddell, Geoff V. Merrett, Ivo N. Ayala-Garcia:
  Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique. 1267-1272
  
• Yaseen Zaidi, Christoph Grimm, Jan Haase:
  Simulation based tuning of system specification. 1273-1278
  
• Chenxu Zhao, Tom J. Kazmierski:
  An extension to SystemC-A to support mixed-technology systems with distributed components. 1278-1284
  
• Elie Maricau, Georges G. E. Gielen:
  Stochastic circuit reliability analysis. 1285-1290
  

Advances in Test Generation and Fault Simulation

• Stephan Eggersglüß, Rolf Drechsler:
  As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. 1291-1296
  
• Irith Pomeranz:
  Built-in generation of functional broadside tests. 1297-1302
  
• Michael A. Kochte, Hans-Joachim Wunderlich:
  SAT-based fault coverage evaluation in the presence of unknown values. 1303-1308
  

Model Based Verification and Synthesis of Embedded Systems

• Sumit Kumar Jha, Christopher James Langmead, Swarup Mohalik, S. Ramesh:
  When to stop verification?: Statistical trade-off between expected loss and simulation cost. 1309-1314
  
• Joost P. H. M. Hausmans, Marco Jan Gerrit Bekooij, Henk Corporaal:
  Resynchronization of Cyclo-Static Dataflow graphs. 1315-1320
  
• Yi-Sheng Chiu, Chi-Sheng Shih, Shih-Hao Hung:
  Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints. 1321-1326
  

Embedded Tutorial - Die Stacking Goes Mobile and Embedded

• Fabien Clermidy, Florian Darve, Denis Dutoit, Walid Lafi, Pascal Vivet:
  3D Embedded multi-core: Some perspectives. 1327-1332
  
• Dongki Kim, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Hyunuk Jung:
  A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC. 1333-1338
  

Panel

• Allan Crone, Oliver Bringmann, C. Chevallaz, B. Dickman, Volkan Esen, M. Rohleder:
  State of the art verification methodologies in 2015. 1339
  

Smart Energy Utilization: From Circuits to Consumer Products

• Alex Yakovlev:
  Energy-modulated computing. 1340-1345
  

Architectural Innovations for Reconfigurable Computing

• Jonghee W. Yoon, Jongeun Lee, Jaewan Jung, Sanghyun Park, Yongjoo Kim, Yunheung Paek, Doosan Cho:
  I²CRF: Incremental interconnect customization for embedded reconfigurable fabrics. 1346-1351
  
• Holger Lange, Thorsten Wink, Andreas Koch:
  MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers. 1352-1357
  
• Fakhar Anjam, Muhammad Nadeem, Stephan Wong:
  Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor. 1358-1363
  

Asynchronous Circuits and Advanced Timing Issues in Logic Synthesis

• Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng:
  An efficient algorithm for multi-domain clock skew scheduling. 1364-1369
  
• Melinda Y. Agyekum, Steven M. Nowick:
  A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication. 1370-1375
  
• Yu Li, Terrence S. T. Mak, Alex Yakovlev:
  Redressing timing issues for speed-independent circuits in deep submicron age. 1376-1381
  

High Level Synthesis

• Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
  Realistic performance-constrained pipelining in high-level synthesis. 1382-1387
  
• Theo Drane, George A. Constantinides:
  Optimisation of mutually exclusive arithmetic sum-of-products. 1388-1393
  
• Kyle Kelley, Megan Wachs, Andrew Danowitz, P. Stevenson, S. Richardon, Mark Horowitz:
  Intermediate representations for controllers in chip generators. 1394-1399
  
• Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
  Power optimization in heterogenous datapaths. 1400-1405
  
• Rohit Sinha, Hiren D. Patel:
  Abstract state machines as an intermediate representation for high-level synthesis. 1406-1411
  

New Directions in Testing

• Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson:
  Design automation for IEEE P1687. 1412-1417
  
• Michael Buttrick, Sandip Kundu:
  On testing prebond dies with incomplete clock networks in a 3D IC using DLLs. 1418-1423
  
• Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
  Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. 1424-1429
  
• Baris Arslan, Alex Orailoglu:
  Adaptive test optimization through real time learning of test effectiveness. 1430-1435
  

Hardware Design for Multimedia Applications

• A. Akin, Ivan Beretta, A. A. Nacci, Vincenzo Rana, Marco D. Santambrogio, David Atienza:
  A high-performance parallel implementation of the Chambolle algorithm. 1436-1441
  
• Christos Kyrkou, Christos Ttofis, Theocharis Theocharides:
  Depth-directed hardware object detection. 1442-1447
  
• Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel:
  Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding. 1448-1453
  

New Frontiers in Embedded Systems Design: Technology and Applications

• Giovanni De Micheli, Sara S. Ghoreishizadeh, Cristina Boero, F. Valgimigli, Sandro Carrara:
  An integrated platform for advanced diagnostics. 1454-1459
  
• Jan Beutel, Bernhard Buchli, Federico Ferrari, Matthias Keller, Marco Zimmerling, Lothar Thiele:
  X-SENSE: Sensing in extreme environments. 1460-1465
  
• Mohamed M. Sabry, Arvind Sridhar, David Atienza, Yuksel Temiz, Yusuf Leblebici, S. Szczukiewicz, N. Borhani, J. R. Thome, Thomas Brunschwiler, Bruno Michel:
  Towards thermally-aware design of 3D MPSoCs with inter-tier cooling. 1466-1471
  
• Qiuting Huang, C. Deholain, C. Enz, Thomas Burger:
  A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative. 1472-1473
  

Stochastic Circuit Reliability Analysis in Nanometer CMOS

• Georges G. E. Gielen, Elie Maricau, Peter H. N. De Wit:
  Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation. 1474-1479
  
• Asen Asenov, Andrew R. Brown, Binjie Cheng:
  Statistical aspects of NBTI/PBTI and impact on SRAM yield. 1480-1485
  
• Eric Remond, Eric Nercessian, Christophe Bernicot, Rayan Mina:
  Mathematical approach based on a "Design of Experiment" to simulate process variations. 1486-1490
  
• Naresh R. Shanbhag, Andrew C. Singer:
  System-assisted analog mixed-signal design. 1491-1496
  

Interactive Presentations

• Hardik Shah, Andreas Raabe, Alois Knoll:
  Priority division: A high-speed shared-memory bus arbitration with bounded latency. 1497-1500
  
• Gilmar S. Beserra, José Edil G. de Medeiros, Arthur M. Sampaio, José Camargo da Costa:
  System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks. 1500-1504
  
• Zhenxin Sun, Chi-Tsai Yeh, Weng-Fai Wong:
  A UML 2-based hardware-software co-design framework for body sensor network applications. 1505-1508
  
• Pankaj Golani, Peter A. Beerel:
  An area-efficient multi-level single-track pipeline template. 1509-1512
  
• Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil Dutt:
  Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. 1513-1516
  
• Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
  Timing variation-aware custom instruction extension technique. 1517-1520
  
• Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
  Pseudo circuit model for representing uncertainty in waveforms. 1521-1524
  
• Zdenek Vasícek, Lukás Sekanina:
  A global postsynthesis optimization method for combinational circuits. 1525-1528
  
• Shuji Tsukiyama, Masahiro Fukui:
  An algorithm to improve accuracy of criticality in statistical static timing analysis. 1529-1532
  
• Tobias Welp, Andreas Kuehlmann:
  An approach for dynamic selection of synthesis transformations based on Markov Decision Processes. 1533-1536
  
• Michael Merrett, Plamen Asenov, Yangang Wang, Mark Zwolinski, Dave Reid, Campbell Millar, Scott Roy, Zhenyu Liu, Stephen B. Furber, Asen Asenov:
  Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. 1537-1540
  

Panel

• P. K. Wright:
  Panel: What does the power industry need from the EDA industry and what is the EDA industry doing about it? 1541
  

Design and Run-Time Support for Dynamic Reconfigurability

• Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker:
  Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. 1542-1547
  
• Ozana Silvia Dragomir, Koen Bertels:
  Loop distribution for K-loops on Reconfigurable Architectures. 1548-1553
  
• Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
  mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions. 1554-1559
  

Reliability and Error Tolerance in Logic Synthesis

• Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram:
  Reliability-driven don't care assignment for logic synthesis. 1560-1565
  
• Doochul Shin, Sandeep K. Gupta:
  A new circuit simplification method for error tolerant applications. 1566-1571
  
• Kai-Chiang Wu, Diana Marculescu:
  Aging-aware timing analysis and optimization considering path sensitization. 1572-1577
  

Multilevel Simulation and Validation

• Feng Lu, Russ Joseph, G. Trajcevski, Song Liu:
  Efficient parameter variation sampling for architecture simulations. 1578-1583
  
• Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
  Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. 1584-1589
  
• Allon Adir, Shady Copty, Shimon Landa, Amir Nahir, Gil Shurek, Avi Ziv, Charles Meissner, John Schumann:
  A unified methodology for pre-silicon verification and post-silicon validation. 1590-1595
  
• Lingyi Liu, Shobha Vasudevan:
  Efficient validation input generation in RTL by hybridized source code analysis. 1596-1601
  
• Salvador Barcelo, X. Gili, Sebastiàn A. Bota, Jaume Segura:
  An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. 1602-1607
  

Error Correction and Resilience

• Chia-Hsiang Chen, Yejoong Kim, Zhengya Zhang, David Blaauw, Dennis Sylvester, H. Naeimi, S. Sandhu:
  A confidence-driven model for error-resilient computing. 1608-1613
  
• Michael Nicolaidis, Thierry Bonnoit, Nacer-Eddine Zergainoh:
  Eliminating speed penalty in ECC protected memories. 1614-1619
  
• Daniele Rossi, N. Timoncini, M. Spica, Cecilia Metra:
  Error correcting code analysis for cache memory high reliability and performance. 1620-1625
  
• Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme:
  Error prediction based on concurrent self-test and reduced slack time. 1626-1631
  

Security Modules from Layout to Network-on-Chip

• Aswin Sreedhar, Sandip Kundu:
  Physically unclonable functions for embeded security based on lithographic variation. 1632-1637
  
• Xuehui Zhang, Mohammad Tehranipoor:
  RON: An on-chip ring oscillator network for hardware Trojan detection. 1638-1643
  
• Marcel Medwed, Stefan Mangard:
  Arithmetic logic units with high error detection rates to counteract fault attacks. 1644-1649
  
• Zhimin Chen, Xu Guo, Ambuj Sinha, Patrick Schaumont:
  Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers. 1650-1655
  

Sustainability through Massively Integrated Computing

• Partha Pratim Pande, Fabien Clermidy, Diego Puschini, Imen Mansouri, Paul Bogdan, Radu Marculescu, Amlan Ganguly:
  Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms? 1656-1661
  

Synthesis Supported Increase of Efficiency in Analog Design

• Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores:
  Automated constraint-driven topology synthesis for analog circuits. 1662-1665
  
• Ralf Sommer, Dominik Krausse, Eckhard Hennig, E. Schaefer, C. Sporrer:
  A new method for automated generation of compensation networks - The EDA Designer Finger. 1666-1672
  
• Volker Boos, Jacek Nowak, Matthias Sylvester, Stephan Henker, Sebastian Höppner, Heiko Grimm, Dominik Krausse, Ralf Sommer:
  Strategies for initial sizing and operating point analysis of analog circuits. 1672-1674
  
• Achim Graupner, Roland Jancke, Reimund Wittmann:
  Generator based approach for analog circuit and layout design and optimization. 1675-1680
  

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