9. DDECS 2006:
Prague, Czech Republic
Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek (Eds.):
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006.
IEEE Computer Society 2006, ISBN 1-4244-0185-2 
Invited Presentations
- Ketan Paranjape:
Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience.
1
- Jaume Segura:
CMOS Testing at the End of the Roadmap: Challenges and Opportunities.
2
Session I - Design Validation
Session II - Physical and IP Design
- Félix Tobajas, Roberto Esper-Chaín, Raúl Regidor, Octavio Santana, Roberto Sarmiento:
A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.
21-26
- Kristian Granhaug, Snorre Aunet:
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology.
27-32
- Abid Rashid, Frank H. P. Fitzek, Ole Olsen, Morten Gade, Yannick Le Moullec:
A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication.
33-38
- András Timár, Ábel Vámos, György Bognár:
Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee Application.
39-43
Session III - Innovative Design Techniques
- Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Borin Soares, Altamiro Amadeu Susin:
A Contextual Resources use: a Proof of Concept through the APACHES' Platform.
44-49
- Zoran Stamenkovic, C. Wolf, Günter Schoof, Jiri Gaisler:
LEON-2: General Purpose Processor for a Wireless Engine.
50-53
- Luca Sterpone, Massimo Violante:
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
54-58
- Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen:
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.
59-64
- Eero Aho, Jarno Vanne, Timo D. Hämäläinen:
Parallel Memory Architecture for Arbitrary Stride Accesses.
65-70
Poster Session I
- Grzegorz Pastuszak:
Architecture Design for the Context Formatter in the H.264/AVC Encoder.
71-72
- Lukas Ruckay:
Recognition of DRM Signal in Frequency Domain and Hardware Demands.
73-74
- V. V. Belkin, S. G. Sharshunov:
ISA Based Functional Test Generation with Application to Self-Test of RISC Processors.
75-76
- Youssef Serrestou, Vincent Beroulle, Chantal Robach:
How to Improve a Set of Design Validation Data by Using Mutation-based Test.
77-78
- Jiri Kadlec, Martin Danek:
Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC.
79-80
- György Bognár, Gyula Horváth, Zoltán Szucs, Vladimir Székely:
Die Attach Quality Testing by Fully Contact-less Measurement Method.
81-82
- Tomás Martínek, Jan Korenek, Otto Fucík, Matej Lexa:
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures.
83-84
- Lukás Sekanina, Lukás Starecek, Zdenek Kotásek:
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules.
85-86
- Harri Lampinen, Pauli Perälä, Olli Vainio:
Design of a Scalable Asynchronous Dataflow Processor.
87-88
- Guoyan Zhang, Ronan Farrell:
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits.
89-90
Student Session I
Session IV - Analog Design
Session V - Analog and Mixed-Signal Test
Poster Session II
- Régis Leveugle, V. Maingot:
On the Use of Information Redundancy When Designing Secure Chips.
141-142
- Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet:
PE-ICE: Parallelized Encryption and Integrity Checking Engine.
143-144
- Martin Novotný, Jan Schmidt:
Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography.
145-146
- Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow.
147-148
- Aki Penttinen, Rafal Jastrzebski, Riku Pölläanen, Olli Pyrhönen:
Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor.
149-150
- Geguang Pu, Jifeng He, Zongyan Qiu:
An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem.
151-152
- Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic, M. Kleszczonek:
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description.
153-154
- Eric Armengaud:
Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems.
155-156
- Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
157-158
- René Kothe, Christian Galke, S. Schultke, H. Froeschke, S. Gaede, Heinrich Theodor Vierhaus:
Hardware/Software Based Hierarchical Self Test for SoCs.
159-160
- Josef Strnadel:
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.
161-162
Session VI - Timing Issues in Design and Test
- Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand:
Design-for-Test of Asynchronous Networks-on-Chip.
163-167
- Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak:
Can Clock Faults be Detected Through Functional Test?
168-173
- André V. Fidalgo, Gustavo R. Alves, José M. Ferreira:
A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns.
174-179
Session VII - Fault Tolerance
- Andrzej Krasniewski:
Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs.
180-185
- Heikki Kariniemi, Jari Nurmi:
Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip.
186-191
- Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
A Flexible SoPC-based Fault Injection Environment.
192-197
- Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt:
Generation and Propagation of Single Event Transients in CMOS Circuits.
198-203
- Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar:
Concurrent Testing of Digital Circuits for Advanced Fault Models.
204-209
- René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube:
Embedded Self Repair by Transistor and Gate Level Reconfiguration.
210-215
Poster Session III
- José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira:
Probabilistic Testability Analysis and DFT Methods at RTL.
216-217
- Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes:
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.
218-219
- S. V. Yarmolik, B. Sokol:
Optimal Memory Address Seeds for Pattern Sensitive Faults Detection.
220-221
- Jirí Jaros, Václav Dvorák:
Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips.
222-223
- Milos Ohlídal, Josef Schwarz:
Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts.
224-225
- Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu:
A Switch Supporting Circuit and Packet Switching for On-Chip Networks.
226-227
- Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz:
FPGA Implementation of a Fast MDCT Algorithm.
228-229
- Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka:
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.
230-231
- Paolo Bernardi, Michelangelo Grosso:
Test Considerations about the Structured ASIC Paradigm.
232-233
- Marco Bucci, Raimondo Luzzi:
A Leakage-based Random Bit Generator with On-line Fault Detection.
234-235
- Vladislav Nagy, Viera Stopjaková:
New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits.
236-237
Student Session II
Session VIII - Memory and Logic Test
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
256-261
- Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
262-267
- Petr Fiser, Hana Kubatova:
Multiple-Vector Column-Matching BIST Design Method.
268-273
- Leos Kafka, Ondrej Novák:
FPGA-based Fault Simulator.
274-278
- F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage.
279-284
- Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.
285-289
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