11. DDECS 2008: Bratislava, Slovakia

Invited Presentations

• Sandip Kundu:
  The Guiding Light for Chip Testing. 1
  
• Krisztián Flautner:
  The Wall Ahead is Made of Rubber. 2
  
• Hans A. R. Manhaeve:
  The Quest for Test: Will Redundancy Cover All? 3
  

Poster Session I

• Dimitar P. Dimitrov:
  Deep-Submicron MOS Transistor Matching: A Case Study. 4-7
  
• Håvard Pedersen Alstad, Snorre Aunet:
  Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. 8-11
  
• Håvard Pedersen Alstad, Snorre Aunet:
  Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. 12-13
  
• Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
  Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. 14-17
  
• Vladimir Havel, Karel K. Vlcek:
  Computation of a nonlinear squashing function in digital neural networks. 18-21
  
• Stanislaw Deniziak, Mariusz Wisniewski:
  An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs. 22-25
  
• Libor Majer, Viera Stopjaková:
  Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes. 26-29
  
• Konstantin V. Shinkarenko, Karel K. Vlcek:
  Design of Erasure Codes for Digital Multimedia Transmitting. 30-33
  
• Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
  Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. 34-37
  

Process Variations Aware Design

• Tomasz Borejko, Witold A. Pleskacz:
  A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. 38-43
  
• Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
  Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling. 44-49
  
• Franz Schlögl, Kerstin Schneider-Hornstein, Horst Zimmermann:
  Gain reduction by gate-leakage currents in regulated cascodes. 50-53
  

Physical Design

• Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke:
  A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. 54-58
  
• Weixun Yan, Horst Zimmermann:
  Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance. 59-63
  
• Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-lung Lo, Wei-Bin Yang, Jiunn-Way Miaw:
  A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. 64-67
  

ATPG and Fault Tolerance

• Daniel Tille, Rolf Drechsler:
  Incremental SAT Instance Generation for SAT-based ATPG. 68-73
  
• Andrzej Krasniewski:
  Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. 74-79
  
• Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
  Analysis of the influence of intermittent faults in a microcontroller. 80-85
  

SoC and NoC Design

• Martin Palkovic, Hans Cappelle, Miguel Glassee, Bruno Bougard, Liesbet Van der Perre:
  Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform. 86-91
  
• Zhonghai Lu, Lei Xia, Axel Jantsch:
  Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. 92-97
  
• Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi:
  MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. 98-103
  
• Stanislaw Deniziak, Robert Tomaszewski:
  Rapid Prototyping of NoC Architectures from a SystemC Specification. 104-109
  

Digital Design Methods

• Zdenek Vasícek, Lukás Sekanina:
  Novel Hardware Implementation of Adaptive Median Filters. 110-115
  
• Padnamabhan Balasubramanian, D. A. Edwards:
  A New Design Technique for Weakly Indicating Function Blocks. 116-121
  
• Petr Fiser, Pemysl Rucký, Irena Vanová:
  Fast Boolean Minimizer for Completely Specified Functions. 122-127
  

Poster Session II

• Grzegorz Janczyk, Tomasz Bieniek:
  The HDL and FE Thermal Modeling of Heterogeneous Systems. 128-131
  
• Zoran Stamenkovic, Goran Panic, Günter Schoof:
  A System-On-Chip for Wireless Body Area Sensor Network Node. 132-135
  
• Frantisek Reznicek:
  Mixed-Signal DFT for fully testable ASIC. 136-139
  
• Karel Dudacek:
  On Minimizing RTOS Aperiodic Tasks Server Energy Consumption. 140-143
  
• Miroslav Manik, Elena Gramatová:
  Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems. 144-145
  
• Virgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu:
  A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. 146-149
  
• Marek Miskowicz:
  Design of Time-to-Digital Converter Output Interface. 150-153
  
• Thilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle:
  Design and Simulation of Runtime Reconfigurable Systems. 154-157
  

ASIC and FPGA Design

• Boyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer:
  Modeling and observing the jitter in ring oscillators implemented in FPGAs. 158-163
  
• Milos Drutarovsky, Michal Varchola:
  Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator. 164-169
  
• Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz:
  Various MDCT implementations in 0.35µm CMOS. 170-173
  

Student Papers

• Kurt Schweiger, Horst Zimmermann:
  Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology. 174-177
  
• Leos Kafka:
  Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs. 178-181
  
• Martin Rozkovec:
  Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits. 182-185
  
• Dilip P. Vasudevan, Aristides Efthymiou:
  A Partial Scan Based Test Generation for Asynchronous Circuits. 186-189
  

Design Verifications

• José Augusto Miranda Nacif, Thiago Silva, Andréa Iabrudi Tavares, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.:
  Efficient Allocation of Verification Resources using Revision History Information. 190-194
  
• Christian Haufe, Frank Rogin:
  Ad-Hoc Translations to Close Verilog Semantics Gap. 195-200
  
• Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee:
  Code Coverage Analysis using High-Level Decision Diagrams. 201-206
  
• Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker:
  Probabilistic Model Checking and Reliability of Results. 207-212
  

Industrial Papers I

• Martin Zádník, Jan Korenek, Petr Kobierský, Ondej Lengál:
  Network Probe for Flexible Flow Monitoring. 213-218
  
• Tomás Martínek, Martin Kosek:
  NetCOPE: Platform for Rapid Development of Network Applications. 219-224
  
• David Smola, Ludk Pantucek:
  IP-based Systematic Design of Power-and Matching-limited Circuits. 225-230
  

Industrial Papers II

• Marco Bucci, Raimondo Luzzi, Santos Torres Vargas:
  A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications. 231-234
  
• Jan Schat:
  Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. 235-240
  
• Jan Schat:
  Evaluation of the Iddq Signature in devices with Gauss-distributed background current. 241-246
  

Poster Session III

• Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec:
  Interconnect Faults Identification and Localization Using Modified Ring LFSRs. 247-250
  
• Dimitrios K. Konstantinou, Michael G. Dimopoulos, Dimitris K. Papakostas, Alkis A. Hatzopoulos, Alexios Spyronasios:
  Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach. 251-254
  
• Lukás Starecek, Lukás Sekanina, Zdenek Kotásek:
  Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. 255-268
  
• Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková:
  Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. 259-262
  
• Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen:
  Diagnosis of Realistic Defects Based on the X-Fault Model. 263-266
  
• Werner Friesenbichler, Thomas Panhofer, Martin Delvai:
  Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. 267-270
  
• Eero Ivask, Jaan Raik, Raimund Ubar:
  Web-Based Framework for Parallel Distributed Test. 271-274
  
• Artur Jutman, Anton Tsertov, Raimund Ubar:
  Calculation of LFSR Seed and Polynomial Pair for BIST Applications. 275-278
  
• Lukas Chruszczyk, Jerzy Rutkowski:
  Excitation optimization in fault diagnosis of analog electronic circuits. 279-282
  
• Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka:
  Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform. 283-286
  

Analog Test

• Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez:
  Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. 287-292
  
• Juraj Brenkus, Viera Stopjaková, Jozef Mihálov:
  Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation. 293-298
  
• Piotr Jantos, Damian Grzechca, Tomasz Golonek, Jerzy Rutkowski:
  The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features. 299-303
  

BIST and Mems Test

• Norbert Dumas, Florence Azaïs, Frédérick Mailly, Andrew Richardson, Pascal Nouet:
  A novel method for test and calibration of capacitive accelerometers with a fully electrical setup. 304-309
  
• Martin Donoval, Martin Daricek, Viera Stopjaková, Juraj Marek:
  On-chip Integration of Magnetic Force Sensing Current Monitors. 310-313
  
• Hao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song:
  A Cost Effective BIST Second-Order Sigma-Delta-Modulator. 314-319
  

SoC and Memory Test

• Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
  SoC Symbolic Simulation: a case study on delay fault testing. 320-325
  
• Michael Higgins, Ciaran MacNamee, Brendan Mullane:
  SoCECT: System on Chip Embedded Core Test. 326-331
  
• Ireneusz Mrozek, Vyacheslav Yarmolik:
  Optimal Backgrounds Selection for Multi Run Memory Testing. 332-338
  
• Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
  Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs. 339-344