13. DDECS 2010: Vienna, Austria

Invited Talks

• Didier Keymeulen:
  Self-repairing and tuning reconfigurable electronics for space. 1
  
• Davide Appello:
  Safety features of SoCs: How can they be re-used? 2
  
• Alex Yakovlev:
  Asynchronous design, Quo Vadis? 3
  

Embedded Tutorials

• Rolf Drechsler, Görschwin Fey:
  Formal verification meets robustness checking - Techniques and challenges. 4
  
• Lukás Sekanina:
  Evolutionary circuit design: Tutorial. 5
  
• Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
  Ensuring high testability without degrading security: Embedded tutorial on "test and security". 6
  
• Said Hamdioui, A. J. van de Goor:
  Advanced embedded memory testing: Reducing the defect per million level at lower test cost. 7
  

Poster Session I

• Christoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton:
  Automated simulation-based verification of power requirements for Systems-on-Chips. 8-11
  
• Stylianos Siskos:
  Noise determination of a current conveyor in an inverting voltage amplifier configuration. 12-15
  
• Fabian Khateb, Dalibor Biolek, Nabhan Khatib, Jiri Vavra:
  Utilizing the Bulk-driven technique in analog circuit design. 16-19
  
• Ali Azarpeyvand, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, Sied Mehdi Fakhraie:
  Instruction reliability analysis for embedded processors. 20-23
  
• Uros Legat, Anton Biasizzo, Franc Novak:
  Automated SEU fault emulation using partial FPGA reconfiguration. 24-27
  
• Nguyen Minh Huu, Bruno Robisson, Michel Agoyan, Nathalie Drach:
  Low-cost fault tolerance on the ALU in simple pipelined processors. 28-31
  
• Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong:
  Design of a single layer programmable Structured ASIC library. 32-35
  
• Luca Sterpone, Niccolò Battezzati:
  On the mitigation of SET broadening effects in integrated circuits. 36-39
  
• Tobias Koal, Heinrich Theodor Vierhaus:
  A software-based self-test and hardware reconfiguration solution for VLIW processors. 40-43
  
• Alberto Villegas, Diego Vázquez, Adoración Rueda:
  A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology. 44-47
  

Advanced Applications of FPGAs

• Boyan Valtchanov, Viktor Fischer, Alain Aubert, Florent Bernard:
  Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs. 48-53
  
• Jan Korenek, Vlastimil Kosar:
  Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching. 54-59
  
• Sebastian Arming, Roman Fenkhuber, Thomas Handl:
  Data compression in hardware - The Burrows-Wheeler approach. 60-65
  

Defect/Fault Tolerance and Evaluation

• Mario Schölzel:
  Software-based self-repair of statically scheduled superscalar data paths. 66-71
  
• Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, J. C. Silva, Pedro Lousã, João Varela:
  Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems. 72-77
  
• Stefan Frehse, Görschwin Fey, Rolf Drechsler:
  A better-than-worst-case robustness measure. 78-83
  

Analog/Mixed, RF Design and Test

• Reinhard Enne, Horst Zimmermann:
  An integrated low power buck converter with a comparator controlled low-side switch. 84-87
  
• Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
  A Build-In Self-Test technique for RF Mixers. 88-92
  
• Yngvar Berg:
  Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors. 93-98
  

Dependable Systems, Reconfiguration and Reliable Operations

• Tobias Koal, Heinrich Theodor Vierhaus:
  Combining de-stressing and self repair for long-term dependable systems. 99-104
  
• Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip. 105-110
  
• Martin Krammer, Federico Clazzer, Eric Armengaud, Michael Karner, Christian Steger, Reinhold Weiss:
  Exploration of the FlexRay signal integrity using a combined prototyping and simulation approach. 111-116
  

Student Poster Session

• Liviu Agnola, Mircea Vladutiu, Mihai Udrescu:
  Self-Adaptive mechanism for cache memory reliability improvement. 117-118
  
• Filip Adamec, Tomas Fryza:
  Design - Time configurable processor basic structure. 119-120
  
• Jan Kloub, Petr Honzík, Martin Danek:
  Reconfigurable hardware objects for image processing on FPGAs. 121-122
  
• Sheng Wu, Xiang Zheng, Zhiqiang Gao, Xiangqing He:
  A 65nm embedded low power SRAM compiler. 123-124
  
• Tomas Mazanec, Antonin Hermanek, Jan Kamenický:
  Blind image deconvolution algorithm on NVIDIA CUDA platform. 125-126
  

Methods in SoC Design

• Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen:
  Partitioning methods for unicast/multicast traffic in 3D NoC architecture. 127-132
  
• Andreas Popp, Andreas Herrholz, Kim Grüttner, Yannick Le Moullec, Peter Koch, Wolfgang Nebel:
  SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures. 133-138
  
• Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg:
  A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip. 139-144
  

Student papers

• Lukás Nagy, Viera Stopjaková:
  Current Sensing Completion Detection in deep sub-micron technologies. 145-148
  
• Jan Kastil, Jan Korenek:
  Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. 149-152
  
• Mehmood-ur-Rehman Awan, Peter Koch:
  Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers. 153-156
  
• Bo Han, Mengmeng Liu, Ning Ge:
  A 3-5GHz UWB CMOS receiver with digital control technique. 157-160
  

Nano-Scale Integration

• Zheng Xie, Doug Edwards:
  Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits. 161-166
  
• Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
  Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. 167-172
  

Student papers

• Martin Straka, Jan Kastil, Zdenek Kotásek:
  Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. 173-176
  
• Piotr Kyziol, Jerzy Rutkowski, Damian Grzechca:
  Testing analog electronic circuits using N-terminal network. 177-180
  
• Libor Majer, Viera Stopjaková:
  The novel approach to wideband RFIC receivers in standard CMOS process. 181-184
  
• C. M. Yang, Hsuan-Ling Kao, Y. C. Chang, M. T. Chen, H. M. Chang, C. H. Wu:
  A low phase noise 20 GHz voltage control oscillator using 0.18-μm CMOS technology. 185-188
  

Poster Session II

• Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila:
  Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. 189-192
  
• Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto:
  SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. 193-196
  
• Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara:
  A synthesis method to propagate false path information from RTL to gate level. 197-200
  
• Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
  How to reduce size of a signature-based diagnostic dictionary used for testing of connections. 201-204
  
• Kurt Schweiger, Horst Zimmermann:
  Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5V. 205-208
  
• Heimo Uhrmann, Lukas Dörrer, Franz Kuttner, Kurt Schweiger, Horst Zimmermann:
  A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS. 209-212
  
• Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz:
  A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. 213-216
  
• Bohumil Klima, Jan Knobloch, Martin Pochyla:
  Intelligent IGBT driver concept for three-phase electric drive diagnostics. 217-220
  
• Amr Helmy, Laurence Pierre, Axel Jantsch:
  Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing. 221-224
  
• Wenbiao Zhou, Per Karlström, Dake Liu:
  NoGap^CL: A flexible common language for processor hardware description. 225-228
  
• Andreas Tockhorn, Claas Cornelius, Hagen Sämrow, Dirk Timmermann:
  Modeling temperature distribution in Networks-on-Chip using RC-circuits. 229-232
  
• Marcus Jeitler, Jakob Lechner, Andreas Steininger:
  Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. 233-236
  

Advanced Digital Architectures

• Martin Danek, Leos Kafka, Lukas Kohout, Jaroslav Sykora:
  Instruction set extensions for multi-threading in LEON3. 237-242
  
• Tatjana Nikolic, Mile K. Stojcev, Zoran Stamenkovic:
  Wrapper design for a CDMA bus in SOC. 243-248
  
• Waqar Hussain, Fabio Garzia, Jari Nurmi:
  Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform. 249-254
  

Memory Testing and Reliability of Memory Elements

• Nicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone:
  Cumulative embedded memory failure bitmap display & analysis. 255-260
  
• A. J. van de Goor, Said Hamdioui, Georgi Gaydadjiev:
  Using a CISC microcontroller to test embedded memories. 261-266
  
• Snorre Aunet, Amir Hasanbegovic:
  Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS. 267-272
  

Poster Session III

• Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki:
  Evaluation of transition untestable faults using a multi-cycle capture test generation method. 273-276
  
• Vaclav Simek, Richard Ruzicka, Lukás Sekanina:
  On analysis of fabricated polymorphic circuits. 281-284
  
• Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang:
  A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. 285-288
  
• Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda:
  A hardware accelerated framework for the generation of design validation programs for SMT processors. 289-292
  
• Edward Hrynkiewicz, Stefan Kolodzinski:
  Non-disjoint decomposition of logic functions in Reed-Muller spectral domain. 293-296
  
• Viktor Pus, Juraj Blaho, Jan Korenek:
  Memory optimizations for packet classification algorithms in FPGA. 297-300
  
• Arash Ahmadpour:
  A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technology. 301-304
  
• Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet:
  A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks. 305-308
  
• Monica Rafaila, Christian Decker, Christoph Grimm, Georg Pelz:
  Simulation-based sensitivity and worst-case analyses of automotive electronics. 309-312
  
• Dominique Gückel, Bastian Schlich, Jörg Brauer, Stefan Kowalewski:
  Synthesizing simulators for model checking microcontroller binary code. 313-316
  

Asynchronous Circuits - Design Verification and Testing

• Werner Friesenbichler, Thomas Panhofer, Andreas Steininger:
  A deterministic approach for hardware fault injection in asynchronous QDI logic. 317-322
  
• Roland Dobai, Elena Gramatová:
  Test pattern generation for the combinational representation of asynchronous circuits. 323-328
  
• Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet:
  Synthesis of asynchronous monitors for critical electronic systems. 329-334
  

Logic Synthesis

• Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
  Synthesizing multiplier in reversible logic. 335-340
  
• Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
  Window optimization of reversible and quantum circuits. 341-345
  
• Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina:
  On logic synthesis of conventionally hard to synthesize circuits using genetic programming. 346-351
  

Test Generation and Diagnosis

• Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko:
  Constraint-based test pattern generation at the Register-Transfer Level. 352-357
  
• Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier:
  Fault diagnosis of crosstalk induced glitches and delay faults. 358-363
  
• Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel:
  Reduction of power dissipation through parallel optimization of test vector and scan register sequences. 364-369
  
• Stefan Erb, Wolfgang Pribyl:
  Comparison of jitter decomposition methods for BER analysis of high-speed serial links. 370-375
  

Applications

• Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
  Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. 376-381
  
• A. J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev:
  Low-cost, customized and flexible SRAM MBIST engine. 382-387
  
• Qing K. Zhu, Joe Yong, Tom Mozdzen:
  Decoupling capacitance study and optimization method for high-performance VLSIs. 388-392
  
• Tomás Urban, Ondrej Subrt, Pravoslav Martínek:
  Versatile sub-bandgap reference IP core. 393-398
  
• Milos Davidovic, Gerald Zach, Horst Zimmermann:
  A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumption. 399-402
  
• Jiri Halak, Sven Ubik, Petr Zejdl:
  Receiver synchronization in video streaming with short latency over asynchronous networks. 403-405
  

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