4. DELTA 2008: Hong Kong

• DongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam:
  A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process. 3-6
  
• Ka Nang Leung, Yanqi Zheng:
  Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads. 7-10
  
• Ka Leong Tsang, George Jie Yuan:
  The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications. 11-14
  
• Hsiu-Ming Huang, Shih-Hsiung Twu, Shih-Jen Cheng, Huang-Jen Chiu:
  A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps. 15-19
  
• Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei:
  Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. 20-25
  
• Jia Li, Qiang Xu, Yu Hu, Xiaowei Li:
  Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. 26-31
  
• Claudia Rusu, Cristian Grecu, Lorena Anghel:
  Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. 32-37
  
• Hans G. Kerkhoff, Jarkko J. M. Huijts:
  Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. 38-44
  
• Jihai Cao, Ning Zhang, Lin Song:
  A Fast Algorithm for the Chirp Rate Estimation. 45-48
  
• Siwaporn Sorncharean, Suebskul Phiphobmongkol:
  Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell Analysis. 49-54
  
• Andrew Gilman, Donald G. Bailey, Stephen Marsland:
  Interpolation Models for Image Super-resolution. 55-60
  
• Sriram Murali, Ramachandran Shankar:
  Performance Analysis of a Vehicle Crash Control System using Image. 61-66
  
• Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu:
  A High Speed CMOS Transmitter and Rail-to-Rail Receiver. 67-70
  
• Won-S. Oh, K. Park, J.-C. Choi, C. J. Kim, S. I. Lee, J. K. Moon:
  Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology. 71-74
  
• Youngkil Choi, Hyungdong Roh, Hyunseok Nam, Jeongjin Roh:
  99-dB High-Performance Delta-Sigma Modulator for 20-kHz Bandwidth. 75-78
  
• Tao Wang, Liping Liang:
  Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR. 79-84
  
• A. Sagahyroon, M. El-Tarhuni, S. Ibrahim:
  An FPGA Implementation of the Searcher Algorithm. 85-88
  
• Amith Kumar Nuggehalli Ramachandra, Avin Kumar Kannur:
  Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System. 89-94
  
• Yaohua Yu, Zhengjie Liu:
  Research on System Usability of Digital Libraries in China. 95-98
  
• Jian Ruan, Chung-Len Lee:
  A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. 99-102
  
• Ki-Jin Kim, K. H. Ahn, T. H. Lim:
  Low Phase Noise Bond Wire VCO for DVB-H. 103-106
  
• Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert:
  A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. 107-110
  
• Liang Shangquan, Gao Minglun, Yin Yongsheng, Deng Honghui:
  A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications. 111-114
  
• Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe:
  A Multiprocessor System for a Small Size Soccer Robot Control System. 115-118
  
• Tero Vallius, Juha Röning:
  Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems. 119-124
  
• Yantu Mo, Suge Yue:
  An Efficient Design of Single Event Transients Tolerance for Logic Circuits. 125-128
  
• Fei Wang, Yu Hu, Xiaowei Li:
  Adaptive Diagnostic Pattern Generation for Scan Chains. 129-132
  
• Jiang Shi, Ricky Smith:
  Built-In Self-Test for Embedded Voltage Regulator. 133-136
  
• Philip Heng Wai Leong:
  Recent Trends in FPGA Architectures and Applications. 137-141
  
• Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos:
  Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. 142-147
  
• Zong Wang, Tughrul Arslan, Ahmet T. Erdogan:
  Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture. 148-152
  
• Xun Zhang, Hassan Rabah, Serge Weber:
  Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC. 153-157
  
• Milos Milosavljevic, Faycal Bensaali, Pandelis Kourtessis:
  xDSL Network Upgrade Employing FPGAs. 158-162
  
• Zhihua Wang, Songping Mai, Chun Zhang:
  Power Issues on Circuit Design for Cochlear Implants. 163-166
  
• Milin Zhang, Amine Bermak:
  Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression. 167-170
  
• W. M. Tang, C. H. Leung, P. T. Lai:
  Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor. 171-174
  
• Hiroshi Ikeoka, Takayuki Hamamoto:
  High Speed Depth Estimation Using Tilted Focal Planes. 175-178
  
• Chi-Hao Wu:
  Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate Driving. 179-183
  
• Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh:
  Dynamic Co-operative Intelligent Memory. 184-189
  
• Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung:
  An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching. 190-195
  
• Omid Mirmotahari, Yngvar Berg:
  Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. 196-200
  
• Bastien Giraud, Amara Amara:
  Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. 201-204
  
• Taehoon Kim, Dongchul Kim, Jung-A Lee, Yungseon Eo:
  Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs. 205-209
  
• Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  Improving Diagnosis Resolution without Physical Information. 210-215
  
• Melanie Po-Leen Ooi, Ye Chow Kuang, Chris Chan, Serge N. Demidenko:
  Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices. 216-221
  
• Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee:
  Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. 222-227
  
• Christopher T. Johnston, Donald G. Bailey:
  FPGA implementation of a Single Pass Connected Components Algorithm. 228-231
  
• Hwang-Cherng Chow, Pu-Nan Weng:
  A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications. 232-235
  
• Hongmoon Wang, Hyun Suk Choi, Jong Tae Kim:
  Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video. 236-239
  
• V. R. Vimal Krishnan, Athulya Jayakumar, Babu Anto P.:
  Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural Network. 240-243
  
• D. Meena, L. G. M. Prakasam:
  FPGA Based Real Time Solution for Sensitivity Time Control. 244-248
  
• Jamiil Tourabaly, Adam Osseiran:
  A Jittered-Sampling Correction Technique for ADCs. 249-252
  
• Kyu-Yeul Wang, Seung-Yerl Lee, Byung-Soo Kim, Sang-Seol Lee, Jae-Yeon Song, Dong-Sun Kim, Duck-Jin Chung:
  Robust JPEG2000 Image Transmission over IEEE 802.15.4. 253-257
  
• Dong-Shong Liang, Kwang-Jow Gan:
  New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. 258-261
  
• Dongchul Kim, Taehoon Kim, Jung-A Lee, Yungseon Eo:
  Experimental Characterisations of Coupled Transmission Lines. 262-265
  
• Bei Cao, Liyi Xiao, Yongsheng Wang:
  A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. 266-269
  
• Jianhua Feng, Guoliang Li:
  A Test Data Compression Method for System-on-a-Chip. 270-273
  
• Te-Jen Su, Chun-Hsiang Kuo, Wen-Pin Tsai, Cheng-Chih Hou:
  A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR Filter. 274-278
  
• Andrea Cuoccio, Paolo Roberto Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
  A Generation Flow for Self-Reconfiguration Controllers Customization. 279-284
  
• Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga:
  Design of High-Speed Floating Point Multiplier. 285-289
  
• Hyun Min Choi, Chun Pyo Hong, Chang Hoon Kim:
  High Performance Elliptic Curve Cryptographic Processor Over GF(2^163). 290-295
  
• Christopher T. Johnston, Paul J. Lyons, Donald G. Bailey:
  A Visual Notation for Processor and Resource Scheduling. 296-301
  
• Nagarajan Venkateswaran, Karthik Chandrasekar, Shrikanth Ganapathy:
  Design for Testability of Functional Cores in High Performance Node Architectures. 302-307
  
• Yong-sheng Cheng, Zhiqiang You, Jishun Kuang:
  Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. 308-313
  
• M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
  AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. 314-321
  
• Gloria Huertas, José Luis Huertas:
  Oscillation-Based Test in Data Converters: On-Line Monitoring. 322-325
  
• Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li:
  A Case Study on At-Speed Testing for a Gigahertz Microprocessor. 326-331
  
• Wen Chang Huang, Jin Chang Cheng, Po Chih Liou:
  A Charge Pump Circuit - Cascading High-Voltage Clock Generator. 332-337
  
• Ngok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui:
  Threshold Voltage Start-up Boost Converter for Sub-mA Applications. 338-341
  
• Chun Yu Cheng, Ka Nang Leung, Yi Ki Sun, Pui Ying Or:
  Design of a Low-Voltage CMOS Charge Pump. 342-345
  
• Wei-Yuan Chiu, Jiun-Wei Horng, Shyuan-Shenq Yang:
  High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCs. 346-350
  
• Bin Zhan, Baochun Hou, Reza Sotudeh:
  Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC Encoder. 351-355
  
• Allen C. Cheng:
  A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads. 356-361
  
• Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue:
  Improved Policies for Drowsy Caches in Embedded Processors. 362-367
  
• Pil Woo Chun, Jamin Islam, Valeri Kirischian, Lev Kirischian:
  Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications. 368-373
  
• Xiaoxiao Zhang, Amine Bermak, Farid Boussaïd, Abdesselam Bouzerdoum:
  A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks. 374-377
  
• Aicha Far, Bin Guo, Farid Flitti, Amine Bermak:
  Temperature Modulation for Tin-Oxide Gas Sensors. 378-381
  
• Moussadek Laadjel, Ahmed Bouridane, Fatih Kurugollu:
  Eigenspectra Palmprint Recognition. 382-385
  
• Camel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane:
  VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. 386-389
  
• Paul Raymond Nicholl, Abbes Amira:
  DWT/PCA Face Recognition using Automatic Coefficient Selection. 390-393
  
• Maxime Ambard, Bin Guo, Dominique Martinez, Amine Bermak:
  A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor Array. 394-397
  
• Thomas Lenart, Henrik Svensson, Viktor Öwall:
  A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. 398-404
  
• Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
  A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. 405-409
  
• Sang Gyun Kim, Woo Sik Kim, Seung Ho Ok, Byung In Moon:
  High-Speed Priority Queue Architecture for Multiple Out Links. 410-414
  
• Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee:
  Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. 415-420
  
• Farid Flitti, Aicha Far, Bin Guo, Amine Bermak:
  Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor Array. 421-424
  
• Marcel Jacomet, Josef Goette, Andreas Eicher:
  On Using Fingerprint-Sensors for PIN-Pad Entry. 425-430
  
• Yan Wang, Amine Bermak, Abdesselam Bouzerdoum, Brian W. Ng:
  FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor Applications. 431-434
  
• Isabell Jahnich, Ina Podolski, Achim Rettberg:
  Integrating Dynamic Load Balancing Strategies into the Car-Network. 435-440
  
• JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong-Hyuk Park, Sang-Sung Choi:
  A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process. 441-445
  
• Zulhakimi Razak, Tughrul Arslan:
  Analog to Digital Converter Specification for UMTS/FDD Receiver Applications. 446-449
  
• Alessio Montone, Marco D. Santambrogio, Donatella Sciuto:
  A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. 450-453
  
• Hariharan Sankaran, Srinivas Katkoori:
  Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. 454-457
  
• Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong:
  Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). 458-461
  
• Minjin Zhang, Huawei Li, Xiaowei Li:
  Static Crosstalk Noise Analysis with Transition Map. 462-465
  
• Si-Woo Kim, Jae-Kyun Lee, Boo-Shik Ryu, Chae-Wook Lee:
  Implementation of the Embedded System for Visually-Impaired People. 466-469
  
• Do Joon Jung, Kyung Su Kwon, Se Hyun Park, Jong Bae Kim, Hang Joon Kim:
  Model-Based Gaze Direction Estimation in Office Environment. 470-473
  
• Stefan Lachowicz, Hans-Jörg Pfleiderer:
  Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. 474-477
  
• Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak:
  Configurable Blocks for Multi-precision Multiplication. 478-481
  
• Shrutisagar Chandrasekaran, Abbes Amira:
  High Performance FPGA Implementation of the Mersenne Twister. 482-485
  
• Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa:
  Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips. 486-490
  
• Xiaojun Zhang, Jiangtao Xi, Yanguang Yu, Joe Chichero:
  The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate Feedback. 491-495
  
• Matthew J. Baker, Jingtai Xi, Joe F. Chicharo:
  Elimination of Gamma Non-linear Luminance Effects for Digital Video Projection Phase Measuring Profilometers. 496-501
  
• Laurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard:
  Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites. 502-505
  
• Kwan Ting Ng, Chen Shoushun, Farid Boussaïd, Amine Bermak:
  Compact Gray-Code Counter/Memory Circuits for Spiking Pixels. 506-511
  
• Amir Zjajo, José Pineda de Gyvez:
  Calibration and Debugging of Multi-step Analog to Digital Converters. 512-515
  
• Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang:
  A Prevenient Voltage Stress Test Method for High Density Memory. 516-520
  
• Hui Liu, Huawei Li, Yu Hu, Xiaowei Li:
  A Scan-Based Delay Test Method for Reduction of Overtesting. 521-526
  
• Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
  An Integrated Validation Environment for Differential Power Analysis. 527-532
  
• Paul Milbredt, Andreas Steininger, Martin Horauer:
  Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. 533-538
  
• Charles Thangaraj, Tom Chen:
  Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. 539-544
  
• Omid Mirmotahari, Yngvar Berg:
  Low Voltage Design against Power Analysis Attacks. 545-548
  
• Moi-Tin Chew, Tatt-Huong Tham, Ye Chow Kuang:
  Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol. 549-554
  
• Saeedeh Bakhshi, Hamid Sarbazi-Azad:
  Efficient VLSI Layout of Edge Product Networks. 555-560
  
• Helene Schilke, Achim Rettberg, Florian Dittmann:
  Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs. 561-566
  
• Weibo Hu, Chung-Len Lee, Xin'an Wang:
  Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. 567-570
  
• Jose Carlos Da Silva, Michal Hujesko, Joao Varela:
  Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter. 571-575
  
• Zhi Yang, Guangsheng Ma, Shu Zhang:
  A Novel Approach to High-Level Property Checking Using Wu's Method. 576-580
  
• Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich:
  Test Set Stripping Limiting the Maximum Number of Specified Bits. 581-586
  
• Weiguang Sheng, Liyi Xiao, Zhigang Mao:
  An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. 587-591
  
• Zsófia Ruttkay, Ton J. Mouthaan:
  CreaTe: A New Programme to Attract Engineers as Design Artists. 592-596
  
• Byung-Heon Kang, Dong-Ho Lee, Chun-Pyo Hong:
  High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular Automata. 597-602
  
• Kyounghwan Lee, Youngju Kim, You Chung Chung:
  Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CST. 603-606
  

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