DFT 1998: Austin, TX, USA

@proceedings{DBLP:conf/dft/1998,
  title     = {13th International Symposium on Defect and Fault-Tolerance in
               VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings},
  booktitle = {DFT},
  publisher = {IEEE Computer Society},
  year      = {1998},
  isbn      = {0-8186-8832-7},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Session 1: Yield and Defect Density

• Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh:
  Binning for IC Quality: Experimental Studies on the SEMATECH Data. 4-10
  
• Leon J. P. Vogels, M. W. C. Dohmen, P. Van Duijvenboden, Robert A. Latimer, J. D. O. Heffernan:
  A Yield Improvement Program Using Process Control and Process Optimization for Particle Reduction Using In Situ Particle Monitoring on a Semitool Magnum. 11-16
  
• Sandrine Barberan, Frederic Duvivier:
  Management of Critical Areas and Defectivity Data for Yield Trend Modeling. 17-
  

Session 2: Layout and Critical Area

• Israel Koren, Zahava Koren:
  Yield and Routing Objectives in Floorplanning. 28-36
  
• Neil Harrison:
  Orphan Metal Removal as an Element of DFM. 37-43
  
• Gerard A. Allan:
  A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation. 44-
  

Session 3: Reliability Enhancement

• Zhan Chen, Fook-Luen Heng:
  A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. 56-63
  
• Glenn H. Chapman:
  FPGA Design for Decimeter Scale Integration (DMSI). 64-72
  
• Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta:
  Process Variations and their Impact on Circuit Operation. 73-
  

Session 4: Defect and Fault Analysis

• Dhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz:
  Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. 84-92
  
• James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
  Characterization of CMOS Defects using Transient Signal Analysis. 93-101
  
• Vijay R. Sar-Dessai, D. M. H. Walker:
  Accurate Fault Modeling and Fault Simulation of Resistive Bridges. 102-107
  
• Xiao Sun, Carmie Hull:
  Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. 108-116
  
• Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera:
  An Integrated HW and SW Fault Injection Environment for Real-Time Systems. 117-
  

Session 5: Testing Techniques

• Claude Thibeault:
  Increasing Current Testing Resolution. 126-134
  
• Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar:
  On-Chip Test Embedding for Multi-Weighted Random LFSRs. 135-
  

Session 6: Testing of Regular Structures

• Avinash Munshi, Fred J. Meyer, Fabrizio Lombardi:
  A New Method for Testing EEPLA's. 146-154
  
• Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas:
  C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. 155-163
  
• Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi:
  On the Complexity of Sequential Testing in Configurable FPGAs. 164-
  

Session 7: Concurrent Testing Techniques

• Cecilia Metra, Michele Favalli, Bruno Riccò:
  Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. 174-182
  
• Donatella Sciuto, Cristina Silvano, Renato Stefanelli:
  Systematic AUED Codes for Self-Checking Architectures. 183-191
  
• Yu-Yau Guo, Jien-Chung Lo:
  Challenges of Built-In Current Sensor Designs. 192-
  

Session 8: Fault Diagnosis

• Claude Thibeault, Luc Boisvert:
  On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. 202-210
  
• Jayabrata Ghosh-Dastidar, Nur A. Touba:
  A Systematic Approach for Diagnosing Multiple Delay Faults. 211-216
  
• Yuejian Wu:
  Diagnosis of Scan Chain Failures. 217-
  

Session 9: Fault-Tolerant Designs I

• W. Lynn Gallagher, Earl E. Swartzlander Jr.:
  Error-Correcting Goldschmidt Dividers Using Time Shared TMR. 224-232
  
• Sergio D'Angelo, Cecilia Metra, Sandro Pastore, A. Pogutz, Giacomo R. Sechi:
  Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. 233-240
  
• Daniel Audet, Steve Masson, Yvon Savaria:
  Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. 241-
  

Session 10: Fault-Tolerant Designs II

• Samuel Norman Hamilton, Alex Orailoglu:
  Transient and Intermittent Fault Recovery without Rollback. 252-260
  
• Jien-Chung Lo:
  Highly Reliable Systems with Differential Built-In Current Sensors. 261-269
  
• Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder:
  A Silicon Compiler for Fault-Tolerant ROMs. 270-275
  
• Susumu Horiguchi, Issei Numata:
  Self-Reconfiguration Scheme of 3D-Mesh Arrays. 276-
  

Session 11: High-Level Synthesis of Reliable Systems

• Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti:
  A System for Evaluating On-Line Testability at the RT-level. 284-291
  
• Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
  High-level Synthesis of Data Paths with Concurrent Error Detection. 292-300
  
• Alex Orailoglu:
  Graceful Degradation in Synthesis of VLSI ICs. 301-311
  
• Marco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini:
  Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis. 312-317
  
• Xiaowei Li, Paul Y. S. Cheung:
  High-Level BIST Synthesis for Delay Testing. 318-
  

Session 12: Yield and Reliability Issues of Analog and Mixed Signal Circuits

• Andrea Boni, Andrea Pierazzi:
  Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs. 326-334
  
• Pramodchandran N. Variyam, Abhijit Chatterjee:
  Specification-Driven Test Design for Analog Circuits. 335-340
  
• Alfred V. Gomes, Ramakrishna Voorakaranam, Abhijit Chatterjee:
  Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity. 341-348
  
• Serge N. Demidenko, Vincenzo Piuri, Vyacheslav N. Yarmolik, A. Shmidman:
  BIST Module for Mixed-Signal Circuits. 349-