DFT 2000: Mt. Fuji, Yamanashi, Japan

15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings. IEEE Computer Society 2000, ISBN 0-7695-0719-0

Yield Analysis and Modeling

Rajnish K. Prasad, Israel Koren:
The Effect of Placement on Yield for Standard Cell Designs. 3-11
Mike Moran, Gerard A. Allan:
IC Critical Volume Calculation through Ray-Casting of CSG Trees. 12-29
Xiaohong Jiang, Susumu Horiguchi, Yue Hao:
Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. 30-

Yield Enhancement Techniques

Tianxu Zhao, Yue Hao, Yong-Chang Jiao:
VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy. 41-46
Nohpill Park, Fred J. Meyer, Fabrizio Lombardi:
Quality-Effective Repair of Multichip Module Systems. 47-55
Israel Koren, Zahava Koren, Glenn H. Chapman:
A Self-Correcting Active Pixel Camera. 56-

Wafer Scale/Large Area Systems

Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. 69-77
Markus Rudack, Michael Redeker, Dieter Treytnar, Ole Mende, Klaus Herrmann:
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications. 78-86
R. M. Lea, P. T. Tetnowski, M. Covic:
A Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing. 87-95
Xiaohong Jiang, Susumu Horiguchi:
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model. 96-104
Klaus Herrmann, Sören Moch, Jörg Hilgenstock, Peter Pirsch:
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. 105-113
Ole Mende, Michael Redeker, Markus Rudack, Dieter Treytnar:
A Multifunctional Laser Linking and Cutting Structure for Standard 0.25 mum CMOS-Technology. 114-

Fault-Tolerant Interconnections

W. Shi, K. Kumar, Fabrizio Lombardi:
On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips. 125-134
Abderrahim Doumar, Hideo Ito:
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. 134-142
Naotake Kamiura, Takashi Kodera, Nobuyuki Matsui:
Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches. 143-

Fault-Tolerant Systems

Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra:
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. 155-163
Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri:
Fault-Tolerant High-Performance Cordic Processors. 164-172
Gian-Carlo Cardarilli, Adelio Salsano, P. Marinucci, Marco Ottavi:
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture. 173-

Error Coding

Masato Kitakami, Hongyuan Chen, Eiji Fujiwara:
Evaluations of Burst Error Recovery for VF Arithmetic Coding. 183-191
Ganesan Umanesan, Eiji Fujiwara:
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. 192-200
Yasunao Katayama, Yasushi Negishi, Sumio Morioka:
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. 201-

Reconfiguration and Repair

Itsuo Takanami:
Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns. 213-221
Nobuo Tsuda:
Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes. 222-230
Alfredo Benso, Silvia Chiusano, Paolo Prinetto, P. Simonotti, G. Ugo:
Self-Repairing in a Micro-Programmed Processor for Dependable Applications. 231-239
Masaru Fukushi, Susumu Horiguchi:
Self-Reconfigurable Mesh Array System on FPGA. 240-

Online Testing

Andreas Steininger, Christoph Scherrer:
How Does Resource Utilization Affect Fault Tolerance? 251-256
Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante:
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. 257-265
Serge N. Demidenko, Eugene M. Levine, Vincenzo Piuri:
Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach. 266-274
Parag K. Lala, Alvernon Walker:
An On-Line Reconfigurable FPGA Architecture. 275-

Built-In Self-Test

Gert Jervan, Zebo Peng, Raimund Ubar:
Test Cost Minimization for Hybrid Bist. 283-291
Giuseppe Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi:
BIST Architectures Selection Based on Behavioral Testing. 292-298
Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai:
BRAINS: A BIST Compiler for Embedded Memories. 299-

Testing Strategies

Nohpill Park, S. J. Ruiwale, Fabrizio Lombardi:
Testing the Configurability of Dynamic FPGAs. 311-319
Sukalyan Mukherjee:
Design for Testability to Achieve High Test Coverage - A Case Study. 320-328
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. 329-337
Janusz Sosnowski, Tomasz Wabia, Tomasz Bech:
Path Delay Fault Testability Analysis. 338-

IDDQ Testing

Madhuban Kishor, José Pineda de Gyvez:
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. 349-357
Shigeru Ohnishi, Michinori Nishihara:
A New Light-Based Logic IC Screening Method. 358-366
Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda:
Testability Analysis of IDDQ Testing with Large Threshold Value. 367-375
Shengli Li, Kai Zhang, Jien-Chung Lo:
The 2nd Order Analysis of IDDQ Test Data. 376-

Fault Injection

Andrea Baldini, Alfredo Benso, Silvia Chiusano, Paolo Prinetto:
'BOND': An Interposition Agents Based Fault Injector for Windows NT. 387-395
Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil:
A Prototype of a VHDL-Based Fault Injection Tool. 396-404
Lörinc Antoni, Régis Leveugle, Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. 405-413
Régis Leveugle:
Fault Injection in VHDL Descriptions and Emulation. 414-

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