DFT 2002: Vancouver, BC, Canada
17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings. IEEE Computer Society 2002 ISBN 0-7695-1831-1
Session 1: Yield I
- Pedram Khademsameni, Marek Syrzycki: Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions. 3-11
- Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi: Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. 12-19
Session 2: Crosstalk Faults
- Pierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. 31-39
- Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park: A Test-Vector Generation Methodology for Crosstalk Noise Faults. 40-50
Session 3: Self-Checking and ABFT
- Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri: A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard. 51-59
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto: Designing Self-Checking FPGAs through Error Detection Codes. 60-68
- Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan: Partially Duplicated Code-Disjoint Carry-Skip Adder. 78-86
- Kartik Mohanram, Nur A. Touba: Input Ordering in Concurrent Checkers to Reduce Power Consumption. 87-98
Session 4: Fault Simulation and Injection I
- Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis: New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. 99-107
- Raoul Velazco, A. Corominas, P. Ferreyra: Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied. 108-116
- Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. 117-128
Session 5: Scan Design
- Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici: Scan Architecture for Shift and Capture Cycle Power Reduction. 129-137
- Ranganathan Sankaralingam, Nur A. Touba: Inserting Test Points to Control Peak Power During Scan Testing. 138-146
- Ching-Hwa Cheng: Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. 147-158
Session 6: Test Application
- Kedarnath J. Balakrishnan, Nur A. Touba: Matrix-Based Test Vector Decompression Using an Embedded Processor. 159-165
- Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi: Data Compression for System-on-Chip Testing Using ATE. 166-176
Session 7: Test Generation
- Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. 177-185
- Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi: Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE. 186-194
- Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey: Testing Digital Circuits with Constraints. 195-206
Session 8: Concurrent Error Detection
- Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale: On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. 207-215
- Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. 216-224
- Francisco Rodríguez, José Carlos Campelo, Juan José Serrano: A Memory Overhead valuation of the Interleaved Signature Instruction Stream. 225-232
- Fabio Salice, Mariagiovanna Sami, Renato Stefanelli: Fault-Tolerant CAM Architectures: A Design Framework. 233-244
Session 9: Fault Simulation and Injection II
- Lörinc Antoni, Régis Leveugle, Béla Fehér: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. 245-253
- Sara Blanc, Joaquin Gracia, Pedro J. Gil: A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. 254-262
- Matteo Sonza Reorda, Massimo Violante: Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. 263-274
Session 10: Interconnect
- Susumu Horiguchi, Yasuyuki Miura: Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH. 275-283
- Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst: Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations. 284-292
Session 11: Yield II
- Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto: Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure. 305-313
- Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault: Yield Modeling of a WSI Telecom Router Architecture. 314-324
Session 12: System-on-Chip Test
- Ozgur Sinanoglu, Alex Orailoglu: Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. 325-333
Session 13: Feasibility of CED
- Thomas Verdel, Yiorgos Makris: Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. 345-353
- Stanislaw J. Piestrak: Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. 354-364
Session 14: Test
- A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza: Emulation-Based Design Errors Identification. 365-371
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Functional Fault Model for FPGA Application-Oriented Testing. 372-380
- Sagar S. Sabade, D. M. H. Walker: Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. 381-389
- Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz: CMOS Standard Cells Characterization for IDDQ Testing. 390-398
- Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala: Neural Networks-Based Parametric Testing of Analog IC. 408-418
Session 15: Reliable and Repairable Memories
- Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri: Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. 419-427
- Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi: Repairability Evaluation of Embedded Multiple Region DRAMs. 428-436
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