DFT 2008: Boston, MA, USA
Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor (Eds.): 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA. IEEE Computer Society 2008
Keynote Talk
- Phil Nigh: The Evolving Role of Test ... it is now a "Value Add" Operation. 3-3
Session 1 - Defect and Fault Tolerance
- Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. 7-15
- Francesco Abate, Massimo Violante: Coping with Obsolescence of Processor Cores in Critical Applications. 24-32
Session 2 - Dependability Analysis and Evaluation
- Oscar Kuiken, Xiao Zhang, Hans G. Kerkhoff: Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications. 45-53
- Franco Fummi, Davide Quaglia, Francesco Stefanni: Network Fault Model for Dependability Assessment of Networked Embedded Systems. 54-62
- Syed Zafar Shazli, Mehdi Baradaran Tahoori: Obtaining Microprocessor Vulnerability Factor Using Formal Methods. 63-71
- Timothy J. Dysart, Peter M. Kogge: System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata. 72-80
Invited Talk
- Kartik Mohanram: Error Detection and Tolerance for Scaled Electronic Technologies. 83-83
Session 3 - Hot Topics
- Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic: Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis. 87-95
- Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker: Built-In Proactive Tuning System for Circuit Aging Resilience. 96-104
- Andrey V. Zykov, Gustavo de Veciana: Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?. 105-113
- Vikas Chandra, Robert C. Aitken: Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS. 114-122
Session 4 - Design for Testability
- Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte: On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. 143-151
- Saurabh Jain, W. Robert Daasch, David Armbrust: Analyzing the Impact of Fault Tolerant BIST for VLSI Design. 152-160
Invited Talk
- Nilanjan Mukherjee: Targeting "Zero DPPM" - Can we ever get there? 163-163
Session 5 - Poster Session
- Waleed K. Al-Assadi, Sindhu Kakarla: A BIST Technique for Crosstalk Noise Detection in FPGAs. 167-175
- Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas: A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. 176-183
- Rui Gong, Kui Dai, Zhiying Wang: A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors. 184-192
- Mahdi Fazeli, Seyed Ghassem Miremadi: A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET. 193-201
- Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren: Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. 202-210
- Glenn H. Chapman, Vijay K. Jain: Defect Tolerance for a Capacitance Based Nanoscale Biosensor. 220-228
- Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker: On Reducing Circuit Malfunctions Caused by Soft Errors. 245-253
- Hongbin Sun, Nanning Zheng, Tong Zhang: Realization of L2 Cache Defect Tolerance Using Multi-bit ECC. 254-262
- Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Soft Error Hardened FF Capable of Detecting Wide Error Pulse. 272-280
- Carlos Arthur Lang Lisbôa, Luigi Carro: XOR-based Low Cost Checkers for Combinational Logic. 281-289
- Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. 290-298
Invited Talk
- Shubu Mukherjee: Architectural Vulnerability Factor (or, does a soft error matter?). 301-301
Session 6 - Reliability and Fault Tolerance
- Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren: Automatic Detection of In-field eld Defect Growth in Image Sensors. 305-313
- Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone: Material Fatigue and Reliability of MEMS Accelerometers. 314-322
- Nilanjan Banerjee, Charles Augustine, Kaushik Roy: Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. 323-331
Session 7 - Error Detection and Correction (I)
- Abhisek Pan, James W. Tschanz, Sandip Kundu: A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. 343-351
- Qiaoyan Yu, Paul Ampadu: Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment. 352-360
- Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni Abramov: Arbitrary Error Detection in Combinational Circuits by Using Partitioning. 361-369
- Prashant D. Joshi: Error Detect Logic Resulting in Faster Address Generate and Decode for Caches. 370-377
Invited Talk
- Zahi S. Abuhamdeh: A Case Study of ATPG Delay Path Performance Based on Measured Power Rail Integrity. 381-381
Session 8 - Testing Techniques
- Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz: ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. 385-393
- Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. 394-402
- Yiwen Shi, Kellie DiPalma, Jennifer Dworak: Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization. 403-411
- Hyunbean Yi, Sandip Kundu: Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. 412-420
Invited Talk
- John E. Savage: Computing at the Nanoscale. 423-423
Session 10 - Error Detection and Correction (2)
- Laura Frigerio, Matteo Alan Radaelli, Fabio Salice: A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation. 427-435
- Salvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano: A Novel Error Detection and Correction Technique for RNS Based FIR Filters. 436-444
- Hamed Tabkhi, Seyed Ghassem Miremadi, Alireza Ejlali: An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors. 445-453
- Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti: Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. 454-462
Session 11 - Testing for Timing and Parametric Failures
- Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam: Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. 465-473
- Yukiya Miura, Jiro Kato: Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. 491-499
Invited Talks
- Kamran Zarrineh: Design for Test Challenges of High Performance/Low Power Microprocessors. 503-503
- Konstantin Likharev: Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits. 504-504
Session 12 - Emerging Technologies
- Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi: A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. 507-515
- Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi: A Tile-Based Error Model for Forward Growth of DNA Self-Assembly. 516-524
- Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi: Checkpointing of Rectilinear Growth in DNA Self-Assembly. 525-533
- Michael T. Niemier, Michael Crocker, Xiaobo Sharon Hu: Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA. 534-542
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last updated on 2013-06-18T211851 by the dblp team