DFT 2009: Chicago, Illinois, USA
Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor (Eds.): 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA. IEEE Computer Society 2009
Keynote Talk
- Michael Campbell: The Future of Test - Product Integration and its Impact on Test. 3
- Sandeep P. Kumar: Low DPM: Why Do We Need it and What Does it Cost! 7
Session 1 - BIST and on-chip test generation
- George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, Foster F. Dai, Victor P. Nelson: Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. 11-19
- Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba: Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. 20-28
- Bradley F. Dutton, Charles E. Stroud: Soft Core Embedded Processor Based Built-In Self-Test of FPGAs. 29-37
- Irith Pomeranz, Sudhakar M. Reddy: On-chip Generation of the Second Primary Input Vectors of Broadside Tests. 38-46
Session 2 - Design for Fault Tolerance I
- Mingjing Chen, Alex Orailoglu: Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience. 49-57
- Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi: A Novel Hardened Design of a CMOS Memory Cell at 32nm. 58-64
Invited Talk
- D. M. H. Walker: Challenges in Delay Testing of Integrated Circuits. 81-82
Session 3 - Emerging technologies
- Nor Zaidi Haron, Said Hamdioui: Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories. 85-93
- Aaron Dingler, M. Jafar Siddiq, Michael T. Niemier, Xiaobo Sharon Hu, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod: Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power. 94-102
- Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi: Coded DNA Self-Assembly for Error Detection/Location. 103-111
- Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi: Errors in DNA Self-Assembly by Synthesized Tile Sets. 112-120
Keynote Talk
- Naveed A. Sherwani: Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. 123-123
Session 4 - Error detection
- Martin Omaña, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska: Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. 127-135
- Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham: SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000. 136-144
- Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin: Reduced Precision Checking for a Floating Point Adder. 145-152
Session 5 - Yield analysis and dependability
- Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren: Characterization of Gain Enhanced In-Field Defects in Digital Imagers. 155-163
- Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang: Analysis of Resistive Open Defects in a Synchronizer. 164-172
- Cristiana Bolchini, Fabrizio Castro, Antonio Miele: A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems. 173-181
- Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe: On the Functional Qualification of a Platform Model. 182-190
Session 6 - Design for Fault Tolerance II
- David Wolpert, Paul Ampadu: A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits. 193-201
- Yueran Gao, Haibo Wang: A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance. 202-210
- Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba: Improving Memory Repair by Selective Row Partitioning. 211-219
Invited Talk
- Hans-Joachim Wunderlich: Software-Based Hardware Fault Tolerance for Many-Core Architectures. 223-223
- Marcelo Lubaszewski: Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? 224-224
Session 7 - Interactive Poster Session
- Takumi Hoshi, Kazuteru Namba, Hideo Ito: Testing of Switch Blocks in Three-Dimensional FPGA. 227-235
- Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue: Reliability and Performance Analysis of FPGA-Based Fault Tolerant System. 245-253
- Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis: An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. 254-262
- Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi: Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. 268-276
- Meng Zhang, Anita Lungu, Daniel J. Sorin: Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. 277-285
- Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino: System Level Testing via TLM 2.0 Debug Transport Interface. 286-294
- Nader Alawadhi, Ozgur Sinanoglu: Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments. 295-303
- Syed Zafar Shazli, Mehdi Baradaran Tahoori: Transient Error Detection and Recovery in Processor Pipelines. 304-312
- Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi: Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels. 313-321
- Yehua Su, Wenjing Rao: Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis. 322-330
- Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud: Complementary Formal Approaches for Dependability Analysis. 331-339
- Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici: Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). 340-348
- Irith Pomeranz, Sudhakar M. Reddy: Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. 358-366
- Yuu Maeda, Haruhiko Kaneko: Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes. 367-375
Keynote Talk
- Norman P. Jouppi: Resilience Challenges for Exascale Systems. 379-379
Session 8 - Testing and Design for Test
- Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Improving the Detectability of Resistive Open Faults in Scan Cells. 383-391
- Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin: An Incremental Approach to Functional Diagnosis. 392-400
- Stelios Neophytou, Maria K. Michael, Kyriakos Christou: Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning. 401-409
- Unni Chandran, Dan Zhao: Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip. 410-418
Invited Talk
- Yiorgos Makris: Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors. 421-421
- Adit D. Singh: A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. 422-422
Session 9 - Error detection and correction
- Salvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano: Error Correction Codes for SEU and SEFI Tolerant Memory Systems. 425-430
- Qiaoyan Yu, Paul Ampadu: Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip. 431-439
- Bo Fu, Paul Ampadu: Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects. 440-448
Invited Talk
- Li-C. Wang: Data Learning Techniques for Functional/System Fmax Prediction. 451-451
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last updated on 2013-06-19T203413 by the dblp team