DSD 2004: Rennes, France

Keynote Speeches

• Pierre G. Paulin:
  Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application. 2-4
  
• Kresimir Mihic, Tajana Simunic, Giovanni De Micheli:
  Reliability and Power Management of Integrated Systems. 5-11
  
• Prabhat Mishra, Nikil D. Dutt:
  Functional Validation of Programmable Architectures. 12-19
  
• Ahmed Amine Jerraya:
  Long Term Trends for Embedded System Design. 20-26
  
• Wolfgang Nebel:
  System-Level Power Optimization. 27-34
  

Invited Papers

• Lech Józwiak:
  Life-Inspired Systems. 36-43
  
• Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero:
  Implicit vs. Explicit Resource Allocation in SMT Processors. 44-51
  
• Ulf Schlichtmann:
  Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance. 52-59
  

Processor and Memory Architectures (S1)

• Roberto R. Osorio, Javier D. Bruguera:
  Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. 62-69
  
• Ahmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland:
  A Simple Micro-Threaded Data-Driven Processor. 70-77
  

Synthesis (HL, LS, PS) (S6)

• Turgay Temel, Avni Morgul, Nizamettin Aydin:
  A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits. 80-87
  
• Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
  Memory Aware HLS and the Implementation of Ageing Vectors. 88-95
  

Processor and Memory Architectures (S2)

• Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin:
  A Complete Methodology for Memory Optimization in DSP Applications. 98-103
  
• P. D. Hyde, G. Russell:
  ASSEC: An Asynchronous Self-Checking RISC-based Processor. 104-111
  
• Huibin Shi, Chris Bailey:
  Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures. 112-120
  
• Chris Bailey:
  A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines. 121-129
  
• Soyeb Alli, Chris Bailey:
  Compiler-Directed Dynamic Memory Disambiguation for Loop Structures. 130-134
  

Synthesis (HL, LS, PS) (S7)

• Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki:
  Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. 136-143
  
• Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke:
  Cost-Efficient Implementation of Adaptive Finite State Machines. 144-151
  
• Petr Fiser, Hana Kubatova:
  Boolean Minimizer FC-Min: Coverage Finding Process. 152-159
  
• Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk:
  An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. 160-167
  
• Görschwin Fey, Junhao Shi, Rolf Drechsler:
  BDD Circuit Optimization for Path Delay Fault Testability. 168-172
  

Applications of (Embedded) Digital Systems (S15)

• Pasquale Ciao, Giulio Colavolpe, Luca Fanucci:
  A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder. 174-181
  
• Luca Fanucci, Riccardo Locatelli, Esa Petri:
  VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers. 182-189
  
• Jayapreetha Natesan, Damu Radhakrishnan:
  Shift Invert Coding (SINV) for Low Power VLSI. 190-194
  
• Jeffrey McFiggins, Marie Yvanoff, Jayanti Venkataraman:
  Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications. 195-199
  
• Jussi Roivainen, Jukka Rautio:
  IP-Block Based Integration of Very High Performance WLAN Modem. 200-207
  

DSP + MISC (S17)

• Ricardo Chaves, Leonel Sousa:
  {2ⁿ+1, s^n+k, sⁿ-1}: A New RNS Moduli Set Extension. 210-217
  
• Muthukumar Venkatesan, Daggu Venkateshwar Rao:
  Image Processing Algorithms on Reconfigurable Architecture using HandelC. 218-226
  
• Imed Aouadi, Omar Hammami:
  Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder. 227-233
  
• Suleyman Malki, Lambert Spaanenburg:
  On the Packet-Switched Implementation of a Discrete-Time CNN. 234-241
  

Special Architectures (S5)

• Luo Jianwen, Jong Ching Chuen:
  Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. 244-248
  
• Umut Küçükkabak, Ahmet Akkas:
  Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson Iteration. 249-253
  
• Faisal M. Khan, Mark G. Arnold, William M. Pottenger:
  Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems. 254-261
  
• Ali R. Iranpour, Krzysztof Kuchcinski:
  Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. 262-269
  

Processor and Memory Architectures (S3)

• Qubo Hu, Martin Palkovic, Per Gunnar Kjeldsberg:
  Memory Requirement Optimization with Loop Fusion and Loop Shifting. 272-278
  
• Vinod Viswanath:
  Multi-log Processor - Towards Scalable Event-Driven Multiprocessors. 279-286
  

Synthesis (S9)

• Lech Józwiak, Szymon Bieganski:
  Information Trans-Coders in Information-Driven Circuit Synthesis. 288-397
  
• S. F. Nielsen, Jens Sparsø, Jan Madsen:
  Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. 298-305
  

SOC (S13)

• Christophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale:
  A Constraints Programming Approach to Communication Scheduling on SoPC Architectures. 308-315
  
• Salim Ouadjaout, Dominique Houzet:
  Easy SoC Design with VCI SystemC Adapters. 316-323
  

Special Architectures (S4)

• Alexander A. Petrovsky, Sergei L. Shkredov:
  Multi-Pipeline Implementations of Real-Time Vector DFT. 326-333
  
• Filippo Speziali, Julien Zory:
  Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders. 334-341
  
• Abdel Ejnioui, Abdelhalim Alsharqawi:
  Pipeline-Level Control of Self-Resetting Pipelines. 342-349
  
• Mars Lan, Morteza Biglari-Abhari:
  An Energy-Efficient Adaptive Multiple-Issue Architecture. 350-357
  
• Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, Burak Okcan:
  A High Speed FPGA Implementation of the Rijndael Algorithm. 358-362
  
• Cao Cao, Bengt Oelmann:
  Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design. 363-370
  

Specification and Modeling (S10)

• Daniel Karlsson, Petru Eles, Zebo Peng:
  A Formal Verification Methodology for IP-based Designs. 372-379
  
• Haridimos T. Vergos, Costas Efstathiou:
  Diminished-1 Modulo 2ⁿ + 1 Squarer Design. 380-386
  
• Miroslaw Jablonski, Marek Gorgon:
  Handel-C implementation of Classical Component Labelling Algorithm. 387-393
  
• David Elléouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin:
  Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. 394-401
  
• Daniel Dietterle, Jerzy Ryman, Kai F. Dombrowski, Rolf Kraemer:
  Mapping of High-Level SDL Models to Efficient Implementations for TinyOS. 402-406
  

Validation / Verification (S12)

• Abdil Rashid Mohamed, Zebo Peng, Petru Eles:
  A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. 408-415
  
• Alexander V. Drozd, R. Al-Azzeh, J. V. Drozd, M. V. Lobachev:
  The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data. 416-423
  
• Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
  Scene Management Models and Overlap Tests for Tile-Based Rendering. 424-431
  
• Piotr Gawkowski, Janusz Sosnowski:
  Evaluation of Transient Fault Susceptibility in Microprocessor Systems. 432-439
  
• Vladimir Hahanov, Irina Hahanova, Stanley Hyduke:
  Topological BDP Fault Simulation Method. 440-443
  
• Hamid Shojaei, Habib Ghayoumi:
  Techniques for Formal Verification of Digital Systems: A System Approach. 444-449
  

Applications of (Embedded) Digital Systems (S16)

• Salvatore Vitabile, Antonio Gentile, Sabato Marco Siniscalchi, Filippo Sorbello:
  Efficient Rapid Prototyping of Image and Video Processing Algorithms. 452-458
  
• Robert Prain, Andrew P. Paplinski:
  A Distributed Arithmetic Online Rotator for Signal Processing Applications. 459-466
  
• Radek Dobias, Hana Kubatova:
  FPGA Based Design of the Railway's Interlocking Equipments. 467-473
  

Specification and Modeling (S11)

• Víctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Pedro P. Carballo, Wido Kruijtzer:
  CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip. 476-483
  
• Liam Noonan, Colin Flanagan:
  Modeling a Network Processor Using Object Oriented Techniques. 484-490
  

SOC (S14)

• Nikolay Kavaldjiev, Gerard J. M. Smit:
  An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-Chip. 492-498
  
• Stanislav Korbel, Vlastimil Jánes:
  Interesting Applications of Atmel AVR Microcontrollers. 499-506
  

Special Architectures (S5)

• Jung-Yup Kang, Jean-Luc Gaudiot:
  A Fast and Well-Structured Multiplier. 508-515
  
• Luiza de Macedo Mourelle, Nadia Nedjah:
  Fast Reconfigurable Hardware for the M-ary Modular Exponentiation. 516-523
  
• Kuspriyanto, Yusrila Y. Kerlooza:
  Towards New Real-Time Processor: The Multioperand MSB-First Real-Time Adder. 524-529
  

MISC + Algorithm (S18)

• Jari Kreku, Jani Penttilä, Janne Kangas, Juha-Pekka Soininen:
  Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor Platform. 532-539
  
• Ivan Blunno, Guy Alain Narboni, Claudio Passerone:
  An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. 540-547
  
• Chichyang Chen, Kuo-Sheng Cheng:
  An Efficient Exponential Algorithm with Exponential Convergence Rate. 548-555
  
• Pedro Trancoso:
  What to Adapt in a High-Performance Microprocessor. 556-563
  

Sensor Networks (S19)

• Matthias Handy, Frank Grassert, Dirk Timmermann:
  DCP: A New Data Collection Protocol for Bluetooth-Based Sensor Networks. 566-573
  
• Jianhong Li, Laxmi Gewali, Henry Selvaraj, Muthukumar Venkatesan:
  Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. 574-578
  
• Matthew D'Souza, Adam Postula:
  Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme. 579-586
  
• Ruimin Huang, Yiannos Manoli:
  Phased Array and Adaptive Antenna Transceivers in Wireless Sensor Networks. 587-592
  

Poster Papers

• Abey Abraham Cohen:
  Addressing architecture for Brain-like Massively Parallel Computers. 594-597
  
• Soyeb Alli, Chris Bailey:
  A Mechanism for Implementing Precise Exceptions in Pipelined Processors. 598-602
  
• Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam:
  Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. 603-606
  
• Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya:
  Dynamic Filter Cache for Low Power Instruction Memory Hierarchy. 607-610
  
• Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi:
  Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. 611-614
  
• Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis:
  A Static Low-Power, High-Performance 32-bit Carry Skip Adder. 615-619
  
• J. D. Kranthi Kumar, S. Srinivasan:
  A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation. 620-623
  
• Maria J. Avedillo, José M. Quintana:
  A Threshold Logic Synthesis Tool for RTD Circuits. 624-627
  

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