ERSA 2008:
Las Vegas,
Nevada,
USA
Toomas P. Plaks (Ed.):
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Las Vegas, Nevada, USA, July 14-17, 2008.
CSREA Press 2008, ISBN 1-60132-064-7 
Keynotes
- Steven A. Guccione:
Multicore Devices: A New Generation of Reconfigurable Architectures.
3-11
Invited Talks and Papers
Panel and Workshop
- David L. Andrews, Jason Agron:
Modeling Abstractions for Next Generation Reconfigurable Computing.
49-56
- Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn Bohner:
Design Productivity for Configurable Computing.
57-66
- Bernard Pottier:
FPGAs or Distributed Systems?
67-75
- John Watson, Steven H. Kelem, Brian Box, Joseph Hassoun, Stephen Wasson, Bob Plunkett, Chris Phillips:
A New Tact in Reconfigurable Computing Research.
76-78
- Chris Eddington:
Industrial Workshop - Architectural Synthesis for Reconfigurable Computing.
79
Adaptive and Dynamically Reconfigurable Systems
- Enno Lübbers, Marco Platzner:
Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.
83-89
- Georges Adouko, François Charot, Christophe Wolinski:
A New High Performance Multi Gigabit String Matching Engine.
90-96
- Kehuai Wu, Esben Rosenlund Hansen, Jan Madsen:
Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures.
97-103
- Erik Anderson, Matthew French, Dong-In Kang:
System on a Programmable Chip Adaptation Through Active Partial Reconfiguration.
104-110
- Edgar Ferrer, Dorothy Bollman:
A New Efficient Architecture for Univariate Polynomial Interpolation Over GF(2m).
111-115
- Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu:
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability.
116-121
- Chris Conger, Ann Gordon-Ross, Alan D. George:
Design Framework for Partial Run-Time FPGA Reconfiguration.
122-128
- Joseph Hassoun, Steve Kelemjoseph, Brian Box, Stephen Wasson, Bob Plunkett, Chris Phillips:
Elemental Computing for High Reliability.
129-135
Reconfigurable Computing for Space Based Applications
- Heather Quinn, Paul Graham, Keith Morgan, Jim Krone, Michael Caffrey, Michael J. Wirthlin:
An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs.
139-145
- Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, Alan D. George:
Multiparadigm Computing for Space-Based Synthetic Aperture Radar.
146-152
- Brian Pratt, Michael Caffrey, Derrick Gibelyou, Paul Graham, Keith Morgan, Michael J. Wirthlin:
TMR with More Frequent Voting for Improved FPGA Reliability.
153-158
- Sandeep K. Venishetti, Ali Akoglu:
Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point Division.
159-165
Reconfigurable System Design Tools and Languages
Multi-Context Devices and Applications
Applications of Reconfigurable Systems
- Kuei-Tsung Shih, Arjun Balachandran, Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George:
Fast Real-Time LIDAR Processing on FPGAs.
231-237
- Zachary K. Baker, Justin L. Tripp:
Gradient Run-length Data Compression for Real-time Airborne Image Processing.
238-244
- Tobias Schumacher, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, Marco Platzner:
A Hardware Accelerator for k-th Nearest Neighbor Thinning.
245-251
- Abdel Ejnioui, Paul Bao:
A Parallel Array to Accelerate GFA Modeling in Video Coding.
252-258
- Scott Lloyd, Quinn Snell:
Qnet: A Modular Architecture for Reconfigurable Computing.
259-265
Short Papers
- Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara:
Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.
269-272
- Adarsha Sreeramareddy, Jeff Josiah, Ali Akoglu:
SCARS: Scalable Self-Configurable Architecture for Reusable Space Systems.
273-276
- Gary Block, Paula Pingree, Yungling Lou:
Selection and Use of Programmable Logic in Flight Applications.
277-280
- Robert Barnes, Aravind Dasu:
Hardware/Software Co-designed Extended Kalman Filter on an FPGA.
281-284
- Arjun K. Pai, Khaled Benkrid:
Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications.
285-288
- Mao Nakajima, Minoru Watanabe:
A 770ns Holographic Reconfiguration of a Four-Context DORGA.
289-292
- Qiwei Zhang, Karel Walters, André B. J. Kokkeler, Gerard J. M. Smit:
Dynamically Reconfigurable FFTs for Cognitive Radio on a Multiprocessor Platform.
293-297
- Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci:
High Performance Double Precision Reduction Circuit Implementation in FPGA.
298-301
Posters
- Mariam Hoseini, Chao You, Mark Pavicic:
A Cellular Automata ASIC for Conformal Computing.
305-306
- Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos:
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system.
307-308
- Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama:
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
309-310
- Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi:
FPGA Schemes with Optimized Routing for the Advanced Encryption Standard.
311-312
- Yidong Liu, Srinivasan Santhanam, Jooheung Lee:
Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study.
313-314
Late Papers
- Laura Sanchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo:
FPGA Resource Management Using Internal RAM as Aata Cache.
317-318
- Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo:
Resource Management for Hw Multitasking in Three Dimensional FPGAs.
319-320
- Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III:
The Viability of Cellular Automata Architectures for General Purpose Computing.
321-333
- Ryan Kastner, Ted Huffmire:
Threats and Challenges in Reconfigurable Hardware Security.
334-345
- Gavin Smith, Grant B. Wigley:
High Level Languages for Reconfigurable Computing: An Equivalent to Third Generation Software Languages?
346-352
Copyright © Sun Nov 8 02:18:26 2009
by Michael Ley (ley@uni-trier.de)
