ERSA 2009:
Las Vegas,
Nevada,
USA
Toomas P. Plaks (Ed.):
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA.
CSREA Press 2009, ISBN 1-60132-101-5 
WORLDCOMP Keynote Speeches - ERSA
ERSA Invited Talks
Invited Panel Session; Adaptive / Evolvable Reconfigurable Computing Systems
Industrial Demo
- Peter Athanas:
Element CXI: Exploring Element Computing in Academia.
101
Adaptive and Dynamically Reconfigurable Systems
- Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor:
The Effect of Parameterization on a Reconfigurable Implementation of PIV.
105-111
- Toru Sano, Yoshiki Saito, Hideharu Amano:
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.
112-118
- Madhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rückert:
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
119-125
- Philip Top, Maya Gokhale:
Application Experiments: MPPA and FPGA.
126-135
- Ying Li, Bridget Benson, Ryan Kastner, Xing Zhang:
Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK.
136-142
Multi-Context Devices and Applications
Reconfigurable System Design Tools and Languages
- Kenneth Rovers, Marcel D. van de Burgwal, Jan Kuper, Gerard J. M. Smit:
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures.
167-173
- Paolo Roberto Grassi, Marco D. Santambrogio, Jens Hagemeyer, Christopher Pohl, Mario Porrmann:
SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.
174-180
- Fernando Rincón, Julio Dondo, Jesús Barba, Francisco Moya, Juan Carlos López:
Supporting Operating Systems for Reconfigurable Computing: A Distributed Service Oriented Approach.
181-187
- Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson:
Harnessing Human Computation Cycles for the FPGA Placement Problem.
188-194
- Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
195-201
Applications of Reconfigurable Systems
- Ray Bittner:
The Speedy DDR2 Controller For FPGAs.
205-211
- Austin Rogers, Aleksandar Milenkovic:
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors.
212-218
- Sumedha Gupta Kodipyaka, Jooheung Lee:
A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration.
219-225
- Zahir Larabi, Yves Mathieu, Stéphane Mancini:
High Efficiency Reconfigurable Cache for Image Processing.
226-232
- Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane:
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware.
233-239
- Andrea Abba, Antonio Manenti, Andrea Suardi, Angelo Geraci, Giancarlo Ripamonti:
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices.
240-246
- Andrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci:
High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method.
247-253
- Hassan Edrees, Brian Cheung, McCullen Sandora, David B. Nummey, Deian Stefan:
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators.
254-260
Short Papers
- Masanori Hariyama, Keita Tanji, Michitaka Kameyama:
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation.
263-266
- Guolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang:
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study.
267-270
- Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
271-274
- Kylan Robinson, José G. Delgado-Frias:
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures.
275-278
- Guojun Dai, Peng Liu, Y. Fun Hu, Geyong Min, Zhigang Gao:
Transformable Vertexes Information based Algorithm for Online Task Placement in Reconfigurable System.
279-282
- Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
283-286
- Santos Lépez-Estrada, René Cumplido:
FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing.
287-290
- Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.
291-294
Posters
- Weisheng Zhao, Christian Gamrat, Yves Lhuillier:
Nanocomputing Block based Multi-Context FPGA.
297-298
- Craig Moore, Harald Devos, Dirk Stroobandt:
Optimizing the FPGA Memory Design for a Sobel Edge Detector.
299-300
- Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management.
301-302
- Qian Ding, William Robinson:
An FPGA Implementation of an Elliptic Curve Cryptosystem Coprocessor over Prime Fields.
303-304
- Shinya Kubota, Minoru Watanabe:
A Multi-Context Programmable Optically Reconfigurable Gate Array.
305-306
- Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara:
Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory.
307-308
Late Papers
- Scott Sirowy, Alessandro Forin:
Lost in Space! Quantifying the Elements of FPGA Speedup.
311-314
- Guillermo Botella Juan, Uwe Meyer-Bäse, Antonio García Ríos, Luís Parrilla Roure:
Improved gradient-based motion estimation on reconfigurable platforms.
315-318
- Mariusz Grad, Christian Plessl:
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX.
319-322
- Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabeghi, Koen Bertels, Georgi Gaydadjiev:
Data path Configuration Time Reduction for Run-time Reconfigurable Systems.
323-327
- Jorge Ortiz:
Area Evaluation for Parallel Execution in Reconfigurable Processor Architectures.
328-331
- Hironobu Morita, Minoru Watanabe:
Alignment compensation method for an optically reconfigurable gate array.
332-333
Copyright © Mon Nov 23 22:36:38 2009
by Michael Ley (ley@uni-trier.de)
