ETS 2010: Prague, Czech Republic

Plenary Presentations

• Michael Campbell:
  Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industry. 9
  
• Abhijit Chatterjee:
  Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance. 10
  

Embedded Tutorials

• Peter Maxwell:
  Adaptive test directions. 12-16
  
• Frank Poehl, Frank Demmerle, Juergen Alt, Hermann Obermeir:
  Production test challenges for highly integrated mobile phone SOCs - A case study. 17-22
  

3D and Multi-Core Test

• Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree:
  Test-architecture optimization for TSV-based 3D stacked ICs. 24-29
  
• Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li:
  A low-cost and scalable test architecture for multi-core chips. 30-35
  
• Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis:
  On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. 36-41
  

RF-Test

• Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir:
  On the use of standard digital ATE for the analysis of RF signals. 43-48
  
• Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir:
  Sensors for built-in alternate RF test. 49-54
  
• Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
  Low-cost signature test of RF blocks based on envelope response analysis. 55-60
  

Post-Silicon Debug and Diagnosis

• Ho Fai Ko, Nicola Nicolici:
  Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. 62-67
  

Memory Test

• Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras:
  Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. 69-74
  
• Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li:
  A low-cost built-in self-test scheme for an array of memories. 75-80
  
• Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
  A two-layer SPICE model of the ATMEL TSTAC^TM eFlash memory technology for defect injection and faulty behavior prediction. 81-86
  

Fault Detection, Tolerance and Identification

• Masoud Zamani, Mehdi Baradaran Tahoori:
  A transient error tolerant self-timed asynchronous architecture. 88-93
  
• Navid Farazmand, Mehdi Baradaran Tahoori:
  Multiple fault diagnosis in crossbar nano-architectures. 94-99
  

Delay Analysis

• Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor:
  Full-circuit SPICE simulation based validation of dynamic delay estimation. 101-106
  
• Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura:
  On estimation of NBTI-Induced delay degradation. 107-111
  

Advanced Test Infrastructure

• Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
  Modified T-Flip-Flop based scan cell for RAS. 113-118
  
• Sachin Dileep Dasnurkar, Jacob A. Abraham:
  Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. 119-124
  

Resistive Bridges and Opens

• Jose Luis Garcia-Gervacio, Víctor H. Champac:
  Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. 126-131
  
• Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
  Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. 132-137
  

BIST

• S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi:
  A reconfigurable online BIST for combinational hardware using digital neural networks. 139-144
  
• Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
  A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. 145-150
  
• Emil Gizdarski:
  Constructing augmented time compactors. 151-156
  

Advanced ADC Testing

• Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff:
  Predicting dynamic specifications of ADCs with a low-quality digital input signal. 158-163
  
• Román Mozuelos, Yolanda Lechuga, Mar Martínez, Salvador Bracho:
  Test of embedded analog circuits based on a built-in current sensor. 164-169
  
• Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner:
  Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. 170-174
  

Design Validation, Test and Debug of Complex Systems

• Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler:
  Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. 176-181
  
• Erik Larsson, Bart Vermeulen, Kees Goossens:
  A distributed architecture to check global properties for post-silicon debug. 182-187
  
• Paula Herber, Marcel Pockrandt, Sabine Glesner:
  Automated conformance evaluation of SystemC designs using timed automata. 188-193
  

Innovative Techniques for Highly Reliable Microprocessor-Based Systems

• Michelangelo Grosso, Wilson J. H. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, J. Velasco Medina:
  A software-based self-test methodology for system peripherals. 195-200
  
• Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese:
  Microprocessor fault-tolerance via on-the-fly partial reconfiguration. 201-206
  
• Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz:
  Scan based speed-path debug for a microprocessor. 207-212
  

Fault Tolerance and Online Testing

• Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante:
  An integrated flow for the design of hardened circuits on SRAM-based FPGAs. 214-219
  

Fault Diagnosis

• Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
  Diagnosis of failing scan cells through orthogonal response compaction. 221-226
  
• Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda:
  An adaptive tester architecture for volume diagnosis. 227-232
  
• Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
  Diagnosis of full open defects in interconnect lines with fan-out. 233-238
  

Posters

• Irith Pomeranz, Sudhakar M. Reddy:
  Input test data volume reduction based on test vector chains. 240
  
• Peter Mrak, Anton Biasizzo, Franc Novak:
  On measurement uncertainty of ADC nonlinearities in oscillation-based test. 241
  
• Johannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner:
  Fast simulation based testing of anti-tearing mechanisms for small embedded systems. 242
  
• Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen:
  New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. 243
  
• S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich:
  Design and implementation of Automatic Test Equipment IP module. 244
  
• Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla:
  Add-on blocks and algorithms for improving stimulus compression. 245
  
• Sezer Gören, H. Fatih Ugurdag, Okan Palaz:
  Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. 246
  
• Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue:
  Hybrid test application in hybrid delay scan design. 247
  
• Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
  Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. 248
  
• Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah:
  Test power reduction in compression-based reconfigurable scan architectures. 249
  
• Shaji Krishnan, Hans G. Kerkhoff:
  Multivariate model for test response analysis. 250
  
• Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
  Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. 251
  
• K. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
  Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. 252
  
• Claus Braun, Hans-Joachim Wunderlich:
  Algorithm-based fault tolerance for many-core architectures. 253
  
• Yu Zhang, Vishwani D. Agrawal:
  A diagnostic test generation system and a coverage metric. 254
  
• Lilia Zaourar, Jihane Alami Chentoufi, Yann Kieffer, Arnaud Wenzel, Frederic Grandvaux:
  A shared BIST optimization methodology for memory test. 255
  
• Yang Jin, Hong Wang, Zhengliang Lv, Shiyuan Yang:
  Pipelined parallel test structure for mixed-signal SoCs. 256
  
• Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
  Setting test conditions for improving SRAM reliability. 257
  
• Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi:
  Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. 258
  
• Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
  Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. 259
  
• Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
  Test pattern selection to optimize delay test quality with a limited size of test set. 260
  
• Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski:
  Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy. 261
  
• Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita:
  Current-based testable design of level shifters in liquid crystal display drivers. 262
  
• Z. Xu, Andrew Richardson, L. Li, M. Begbie, D. Koltsov, C. H. Wang:
  A multi-mode MEMS sensor design to support system test and health & usage monitoring applications. 263
  
• Samed Maltabas, Osman Kubilay Ekekon, Martin Margala:
  A new built-in IDDQ testing method using programmable BICS. 264
  
• Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev:
  Defect filter for alternate RF test. 265-270
  

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