EWDTS 2010: St. Petersburg, Russia
2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010. IEEE 2010 ISBN 978-1-4244-9555-9- Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova: An approach for PSL assertion coverage analysis with high-level decision diagrams. 13-16
- Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra: Secure communication protocol for wireless sensor networks. 17-20
- Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski: Hardware reduction for FSM - Based control units using PAL technology. 21-24
- Liudmila D. Cheremisinova, Dmitry Ya. Novikov: SAT-based group method for verification of logical descriptions with functional indeterminacy. 25-28
- Sargis Abovyan, Gor Petrosyan, Tigran Harutyunyan: Architecture of queued-free crossbar for on-chip networks. 34-36
- Gor Petrosyan, Sargis Abovyan, Tigran Harutyunyan: Modeling on-chip variations in digital circuits using statistical timing analysis. 37-39
- V. Melikyan, S. Karapetyan, D. Mirzoyan, E. Babayan: Stable current and voltage generation under process variation. 40-42
- Janusz Sosnowski: Self-testing of microcontrollers in the field. 43-46
- Stefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto: Exploring modeling and testing of NAND flash memories. 47-50
- Vladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz: Coverage method for FPGA fault logic blocks by spares. 51-56
- Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: Experiments with ABIST test methodology applied to path delay fault testing. 59-63
- Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan: Improving reliability for bit parallel finite field multipliers using Decimal Hamming. 69-72
- Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski: Microprogram control unit with code sharing and extended microinstruction format. 73-76
- Vladimir Hahanov, Irina Hahanova, Ngene Christopher Umerah, Tiecoura Yves: Testing and verification of HDL-models for SoC components. 77-82
- Branka Medved Rogina, Peter Skoda, Karolj Skala, Ivan Michieli, Maja Vlah, Sinisa Marijan: Metastability testing at FPGA circuit design using propagation time characterization. 80-85
- A. Andrashov, Vyacheslav S. Kharchenko, Vladimir V. Sklyar, L. Reva, V. Dovgopolyi, V. Golovir: Verification of FPGA electronic designs for nuclear reactor trip systems: test- and invariant-based methods. 92-97
- Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko: Cyber space and brain-like computing. 98-109
- Vladimir Hahanov, Wajeb Gharibi, Svetlana Chumachenko, Eugenia Litvinova: Vector logic analysis of associative matrices. 110-117
- Vladimir Hahanov, Eugenia Litvinova, Aleksey Priymak: Table data structures for cyber space. 118-122
- Vladimir Hahanov, Olesya Guz, Ngene Christopher Umerah, Vitaliy Olchovoy: Process models for analyzing associative data structures. 123-127
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov: A technique to accelerate the Vector Fitting algorithm for interconnect simulation. 127-130
- Mark M. Gourary, Sergey G. Rusakov, Alexander L. Stempkovsky, Sergey L. Ulyanov, Michael M. Zharov: Frequency domain techniques for simulation of oscillators. 131-134
- Alexander Drozd, Vyacheslav S. Kharchenko, Siora Alexandr, Vladimir V. Sklyar: Component-based safety-oriented on-line testing of digital systems. 135-140
- F. Podyablonsky, N. Kascheev: Generalized faulty block model for automatic test pattern generation. 141-143
- Natalia V. Chebykina, Sergey G. Mosin: A technique of optimal built-in self-test circuitries generation. 145-148
- Victor I. Djigan: Applied library of adaptive lattice filters for nonstationary signal processing. 149-152
- Andrey Zakonov, Oleg Stepanov, Anatoly Shalyto: GA-based and design by contract approach to test generation for EFSMs. 152-155
- Vladislav A. Lesnikov, Tatiana V. Naumovich, Alexander V. Chastikov, Sergey V. Armishev: Implementation of a new paradigm in design of IIR digital filters. 156-159
- Anjela Matrosova, E. Nikolaeva: PDFs testing of combinational circuits based on covering ROBDDs. 160-163
- Valentina Andreeva: Test minimization technique for multiple stuck-at faults of combinational circuit. 168-170
- S. Ostanin, R. Muchamedov: Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function. 171-174
- G. S. Khanyan: Level quantization effect on accuracy of fast Fourier transform algorithm. 175-178
- S. O. Churayev, B. T. Matkarimov, T. T. Paltashev: On-chip measurements of standard-cell propagation delay. 179-181
- Volodymyr Obrizan: A method for automatic generation of an RTL-interface from a C++ description. 186-189
- Aleksandr V. Shishkin: OFDM-based audio watermarking for electronic radiotelephone identification. 190-194
- George Dan Mois, Iulia Stefan, Szilárd Enyedi, Liviu Miclea: Reconfiguration and hardware agents in testing and repair of distributed systems. 195-198
- Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh: On selection of state variables for delay test of identical functional units. 200-203
- Vladimir Hahanov, Alexander Mishchenko, Vitaliy Varetsa: Metrics of vector logic algebra for cyber space. 204-207
- Vladimir Hahanov, Irina Pobizhenko, Tiecoura Yves: Logical method for detecting faults by fault detection table. 215-217
- Stefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto: EDACs and test integration strategies for NAND flash memories. 218-221
- Nadereh Hatami, Marco Indaco, Paolo Prinetto, Gabriele Tiotto: Communication interface synthesis from TLM 2.0 to RTL. 222-226
- Nadereh Hatami, Paolo Prinetto, Gabriele Tiotto: Sign Language synthesis using hand motion acquisition. 226-229
- Victor V. Panteleev: An algorithm of timing recovery for modem with M-ary alphabets APK-signals. 230-235
- Victor V. Panteleev, Alexander I. Vakaruk: Engineering-maintenance methods of the calculation xDSL-lines. 236-241
- Sergei G. Krutchinsky, Michael S. Tsibin, Alexey E. Titov: Common-mode signal minimization in differential stage. 242-245
- Sergei G. Krutchinsky: Optimization of sensitivity dominating parameters OA in selective IP blocks. 246-249
- Irina D. Pletneva, Victor I. Djigan: Adaptive array based on "Multicore" DSP family and Linearly Constrained constant modulus IQRD RLS algorithm. 254-257
- Victor I. Djigan: Performance investigation of antenna arrays by means of virtual instruments. 258-261
- G. S. Khanyan: Level quantization effects in digital signal processing by discrete Fourier transform method. 262-265
- Igor Ilyin, Rostislav Grushvitsky: Internal structure of software application for controlling devices via JTAG 1149 interface. 264-266
- Vladimir Volkov, Rudolf Germer, Alexandr Oneshko, Denis Oralov: Straight edge extraction and localization on noisy images. 267-270
- Stanislav S. Gritsutenko, Aleksey G. Panyukov: Quantization step dispersion of direct transformation ADC. 274-277
- Alexander B. Sergienko, Alexander V. Petrov: Blind carrier frequency offset estimation for QAM signals based on weighted 4th power of signal samples. 278-281
- Vladislav A. Lesnikov, Tatiana V. Naumovich, Alexander V. Chastikov, Sergey V. Armishev: A new paradigm in design of IIR digital filters. 282-285
- Y. A. Skobtsov, V. Y. Skobtsov: Evolutionary approach to test generation of sequential digital circuits with multiple observation time strategy. 286-291
- H. V. Kharchenko, I. O. Tkalich, Y. I. Vdovychenko: Two-criterial DSSS synchronization method efficiency research. 289-299
- Dmitriy Speranskiy: An entropic approach to diagnostic information compression. 292-299
- Alexander Zemliak, M. Torres, F. Reyes, S. Vergara, T. M. Markina: Dynamic characteristics of different system design strategies. 300-303
- Yegor I. Vdovychenko: FPGA-based digital phase difference meter. 309
- H. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian: An efficient March test for detection of all two-operation dynamic faults from subclass Sav. 310-313
- H. H. Asadov, Y. N. Aliyeva, L. A. Bayramova, K. Kh. Ismailov: New method of multi-level optimization. 319-321
- H. H. Asadov, N. A. Abdullayev, M. J. Kerimov, E. F. Dadashov: Utilization of variation optimization for location of emitter of random noise signal. 322-323
- H. H. Asadov, N. A. Abdullayev, E. A. Ibrahimov, V. M. Garayev, E. Abbaszadeh: Information optimization of distributed net of receivers of acoustic noise type signals. 324-325
- H. H. Asadov, N. A. Abdullayev, I. K. Agayev, N. A. Nabiyev, R. T. Rajabli: Optimization of information - Measuring systems of non-stationary operational regime in multiple measurements mode. 326-327
- H. H. Asadov, N. A. Abdullayev, S. B. Jalilov, N. A. Nabiyev, N. H. Javadov: On possibility of stabilizing results for multicriteria optimizing linear combination of concurrent functionals. 328-329
- Viney Kumar, Rahul Raj Choudhary, Virendra Singh: FREP: A soft error resilient pipelined RISC architecture. 330-333
- Vitalij Pavlenko, Viktor Burdeinyi: Cluster computing framework based on transparent parallelizing technology. 339-342
- N. S. Vinay, Indira Rawaty, Erik Larsson, M. S. Gaur, Virendra Singh: Thermal aware test scheduling for stacked multi-chip-modules. 343-349
- K. R. Vinutha, Virendra Singh, Anzhela Matrosova, M. S. Gaur: Fault grading using Instruction-Execution graph. 350-357
- A. A. Bykau, I. I. Piletsky: Internet applications testing automation through probabilistic-network programming. 362-365
- Mudar Almadi, Diaa Moamar, Vladimir Ryabtsev: Methodology of algorithms synthesis of storage devices test diagnosing. 366-370
- Nina Khairova, Natalia Sharonova: Building of the logic network of the information area of the corporation. 371-373
- Eduard Atkin, Yuri Volkov, Alexander Klyuev, Vitaly Shumihin: Development of the data-driven readout ASIC for microstrip detectors. 374-375
- Nina Khairova, Natalia Sharonova: Use of predicate categories for modelling of operation of the semantic analyzer of the linguistic processor. 382-385
- Alexander Drozd, Svetlana Antoshchuk, A. Martinuk, J. Drozd: Increase in reliability of on-line testing methods using natural time redundancy. 386-391
- Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski: Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. 390-394
- Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi: A TLM2.0 assertion library with centralized monitoring approach. 402-406
- Vazgen Melikyan, Aristakes Hovsepyan, Tigran Harutyunyan: Schematic protection method from influence of total ionization dose effects on threshold voltage of MOS transistors. 407-409
- Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi: Virtual tester development using HDL/PLI. 412-415
- Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi: Merit based directed random test generation (MDRTG) scheme for combinational circuits. 416-419
- Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi: Near optimal machine learning based random test generation. 420-424
- Alexander Adamov, Vladimir Hahanov: Security risks in hardware: Implementation and detection problem. 425-427
- Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi: Facilitating testability of TLM FIFO: SystemC implementations. 428-431
- Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi: Code optimization for enhancing SystemC simulation time. 431-434
- Vazgen Melikyan, Karen Sahakyan, Armen Nazaryan: 5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technology. 434-437
- Dmitri Boulytchev, Oleg Medvedev: Hardware description language based on message passing and implicit pipelining. 438-441
- Mikhail Talalay, Konstantin Trushin, Oleg Venger: Between standard cells and transistors: Layout templates for Regular Fabrics. 442-448
- Alexander Adamov, Alexander Saprykin: The problem of Trojan inclusions in software and hardware. 449-451
- Vitaliy Kulanov, Vyacheslav S. Kharchenko, Artem Perepelitsyn: Parameterized IP Infrastructures for fault-tolerant FPGA-based systems: Development, assessment, case-study. 452-455
- Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi: Generating test patterns for sequential circuits using random patterns by PLI functions. 456-461
- M. H. Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi: Low cost error tolerant motion estimation for H.264/AVC standard. 461-465
- A. S. Epifanov: Method of diagnosing FPGA with use of geometrical images. 465-468
- Vladimir Hahanov, Aleksey Sushanov, Yulia Stepanova, Alexander Gorobets: System in Package. Diagnosis and embedded repair. 468-472
- Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova, Oleg Zakharchenko, Natalya Kulbakova: Technology for faulty blocks coverage by spares. 473-478
- Vladimir Hahanov, Sergey Galagan, Vitaliy Olchovoy, Aleksey Priymak: Algebra-logical repair method for FPGA logic blocks. 482-487
- Mikhail M. Chupilko: Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models. 487-490
- Somayyeh Jafarali Jassbi, Mehdi Hosseinzade, Keivan Navi: Redundant Multi-Level one-hot Residue Number System based error correction codes. 491-494
- Sergey Mikhtonyuk, Maksim Davydov, Roman Hwang, Dmitry Shcherbin: IEEE 1500 compliant test wrapper generation tool for VHDL models. 495-499
- Dmitry Melnik, Olga Lukashenko, Sergey Zaychenko: Early detection of potentially non-synchronized CDC paths using structural analysis technique. 500-503
- M. H. Haghbayan, Zainalabedin Navabi: Architecture design and technical methodology for bus testing. 504-509
- Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi: Assertion based verification in TLM. 509-513
- Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus: Advanced topics of FSM design using FPGA educational boards and web-based tools. 514-517
- Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi: A mixed HDL/PLI test package. 518-523
- Muhammad Mehdi Lotfinejad, Mohammad Mosleh, Hamid Noori: A novel high speed residue to binary converter design based on the three-moduli set {2n, 2n+1+1, 2n+1-1}. 524-526
- V. A. Tverdokhlebov: Phase pictures of properties of complex objects of technical diagnostics. 527-530
- Yevgeniya Sulema, Samira Ebrahimi Kahou: Image compression: Comparative analysis of basic algorithms. 534-537
- A. I. Petrenko: Networked VLSI and MEMS designer for Grid. 538-544
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last updated on 2013-06-19T203413 by the dblp team