3. FCCM 1995: Napa, CA, USA

3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA. IEEE Computer Society 1995

Custom Computing Platforms

Art Lew, Richard P. Halverson Jr.:
A FCCM for dataflow (spreadsheet) programs. 2-10
Thomas H. Drayer, Joseph G. Tront, William E. King IV, Richard W. Conners:
MORRPH: a modular and reprogrammable real-time processing hardware. 11-19
Javier Moran Carrera, Eduardo Juarez Martinez, S. A. Fernandez, J. M. M. Chaus:
Architecture of a FPGA-based coprocessor: the PAR-1. 20-31

Custom Computing Platforms

Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider:
Teramac-configurable custom computing. 32-38
Brian A. Box, J. Nieznanski:
Common processor element packaging for CHAMP. 39-44
H. Högl, Andreas Kugel, J. Ludvig, Reinhard Männer, K. H. Noffz, R. Zoz: Enable ++: A Second Generation FPGA Processor. 45-55

Signal Transport

Chun-Chao Yeh, Chun-Hsing Wu, Jie-Yong Juang:
Design and implementation of a multicomputer interconnection network using FPGAs. 56-60
Jianmin Li, Chung-Kuan Cheng:
Routability improvement using dynamic interconnect architecture. 61-67
Kazuhiro Hayashi, Toshiaki Miyazaki, Kazuhiro Shirakawa, Kazuhisa Yamada, Naohisa Ohta:
Reconfigurable real-time signal transport system using custom FPGAs. 68-77

Run-Time Reconfiguration

James D. Hadley, Brad L. Hutchings:
Design methodologies for partially reconfigured systems. 78-84
Brian Schoner, Christopher R. Jones, John D. Villasenor:
Issues in wireless video coding using run-time-reconfigurable FPGAs. 85-89
Eric Lemoine, David Merceron:
Run time reconfiguration of FPGA for scanning genomic databases. 90-98
Michael J. Wirthlin, Brad L. Hutchings:
A dynamic instruction set computer. 99-109

Applications I

Richard W. Wieler, Zaifu Zhang, Robert D. McLeod:
Emulating static faults using a Xilinx based emulator. 110-115
Michael Dao, Todd A. Cook, Deborah Silver, Paul S. D'Urbano:
Acceleration of template-based ray casting for volume visualization using FPGAs. 116-124
Mark Shand:
Flexible image acquisition using reconfigurable hardware. 125-135

Compiler Issues I

David R. Galloway:
The Transmogrifier C hardware description language and compiler for FPGAs. 136-144
Satnam Singh:
Architectural descriptions for FPGA circuits. 145-154
Nabeel Shirazi, Al Walters, Peter M. Athanas:
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines. 155-163

Compiler Issues II

W. Luk:
A declarative approach to incremental custom computing. 164-172
Christian Iseli, Eduardo Sanchez:
A C++ compiler for FPGA custom execution units synthesis. 173-179
Nathan Sitkoff, Michael E. Wazlowski, Aaron Smith, Harvey F. Silverman:
Implementing a genetic algorithm on a parallel custom computing machine. 180-189

Applications II

Russell D. Meier:
Rapid prototyping of a RISC architecture for implementation in FPGAs. 190-196
H. A. Chow, Hussein M. Alnuweiri, Steve Casselman:
FPGA-based transformable computers for fast digital signal processing. 197-203
Nalini K. Ratha, Anil K. Jain, Diane T. Rover:
Convolution on Splash 2. 204-213
Herman Schmit, Donald E. Thomas:
Hidden Markov modeling and fuzzy controllers in FPGAs. 214-221

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