15. FCCM 2007: Napa, CA, USA

Applications

• David B. Thomas, Wayne Luk:
  Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. 3-12
  
• Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos:
  A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem. 13-22
  
• Zachary K. Baker, Maya Gokhale:
  On the Acceleration of Shortest Path Calculations in Transportation Networks. 23-34
  

Software Tools

• Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
  Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. 35-44
  
• Adam Megacz:
  A Library and Platform for FPGA Bitstream Manipulation. 45-54
  

System

• Michael Butts, Anthony Mark Jones, Paul Wasson:
  A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing. 55-64
  
• Christoforos Kachris, Chidamber Kulkarni:
  Configurable Transactional Memory. 65-72
  
• Philip Garcia, Katherine Compton:
  A Reconfigurable Hardware Interface for a Modern Computing System. 73-84
  

Bioinformatics

• Jason D. Bakos:
  FPGA Acceleration of Gene Rearrangement Analysis. 85-94
  
• Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain:
  FPGA-accelerated seed generation in Mercury BLASTP. 95-106
  

Scientific Computing

• Kentaro Sano, Takanori Iizuka, Satoru Yamamoto:
  Systolic Architecture for Computational Fluid Dynamics on FPGAs. 107-116
  
• Yongfeng Gu, Martin C. Herbordt:
  FPGA-Based Multigrid Computation for Molecular Dynamics Simulations. 117-126
  
• Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka:
  Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing. 127-140
  

Applications

• Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung:
  Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. 141-150
  
• Xiaojun Wang, Miriam Leeser:
  K-means Clustering for Multispectral Images Using Floating-Point Divide. 151-162
  

Floating Point Arithmetic

• Haohuan Fu, Oskar Mencer, Wayne Luk:
  Optimizing Logarithmic Arithmetic on FPGAs. 163-172
  
• Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson:
  Generating FPGA-Accelerated DFT Libraries. 173-184
  
• Ronen Goldberg, Guy Even, Peter-Michael Seidel:
  An FPGA implementation of pipelined multiplicative division with IEEE Rounding. 185-196
  

Applications

• Giacomo de Meulenaer, François Gosset, Guerric Meurice de Dormale, Jean-Jacques Quisquater:
  Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable Hardware. 197-206
  
• Zachary K. Baker, Maya B. Gokhale, Justin L. Tripp:
  Matched Filter Computation on FPGA, Cell and GPU. 207-218
  

Software Tools II

• Rui Rodrigues, João M. P. Cardoso, Pedro C. Diniz:
  A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops. 219-228
  
• Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King:
  Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. 229-238
  
• Volodymyr V. Kindratenko, Robert J. Brunner, Adam D. Myers:
  Mitrion-C Application Development on SGI Altix 350/RC100. 239-250
  

Optimization

• Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
  Automatic On-chip Memory Minimization for Data Reuse. 251-260
  
• Kyle Rupnow, Keith D. Underwood, Katherine Compton:
  Scientific Application Acceleration with Reconfigurable Functional Units. 261-274
  

Posters

• Khaled Benkrid, Ying Liu, Abdsamad Benkrid:
  Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. 275-278
  
• Charles Ross, A. P. Wim Böhm:
  The Case for Dynamic Execution on Dynamic Hardware. 279-280
  
• Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater:
  On Solving RC5 Challenges with FPGAs. 281-282
  
• Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann:
  Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. 283-284
  
• Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi:
  A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. 285-286
  
• Tim Güneysu, Bodo Möller, Christof Paar:
  New Protection Mechanisms for Intellectual Property in Reconfigurable Logic. 287-288
  
• Thomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier:
  Establishing Chain of Trust in Reconfigurable Hardware. 289-290
  
• F. Javier Toledo-Moreo, J. Javier Martínez-Álvarez, José Manuel Ferrández de Vicente:
  Hand-based Interface for Augmented Reality. 291-292
  
• J. Javier Martínez-Álvarez, F. Javier Toledo-Moreo, José Manuel Ferrández de Vicente:
  Discrete-Time Cellular Neural Networks in FPGA. 293-294
  
• Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes:
  Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. 295-296
  
• Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan:
  Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems. 297-298
  
• Proshanta Saha, Tarek A. El-Ghazawi:
  Software/Hardware Co-Scheduling for Reconfigurable Computing Systems. 299-300
  
• Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan:
  Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures. 301-304
  
• Graham Schelle, Dirk Grunwald:
  Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources. 305-308
  
• Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi:
  A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. 309-310
  
• Love Singhal, Elaheh Bozorgzadeh:
  Heterogeneous Floorplanner for FPGA. 311-312
  
• Neil W. Bergmann, Yi Lu, John A. Williams:
  Automatic Self-Reconfiguration of System-on-Chip Peripherals. 313-316
  
• Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
  A Hybrid Memory Sub-system for Video Coding Applications. 317-318
  
• I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler:
  Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. 319-320
  
• Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo:
  PixelStreams-based implementation of videodetector. 321-322
  
• Euripides Sotiriades, Apostolos Dollas:
  Design Space Exploration for the BLAST Algorithm Implementation. 323-326
  
• Grigorios Chrysos, Apostolos Dollas, Nikolaos G. Bourbakis, J. Sukarno Mertoguno:
  An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology. 327-330
  
• Wanda Gay, Clay S. Gloster Jr.:
  A Configurable Processor Synthesis System. 331-332
  
• Chris Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang:
  Low-Cost Stereo Vision on an FPGA. 333-334
  
• Kyprianos Papadimitriou, Antonis Anyfantis, Apostolos Dollas:
  Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead. 335-336
  
• Andrew G. Schmidt, Ron Sass:
  Quantifying Effective Memory Bandwidth of Platform FPGAs. 337-338
  
• Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel:
  A Flexible Filter Processor for Fading Channel Simulation. 339-342
  
• Kushal Datta, Ron Sass:
  RBoot: Software Infrastructure for a Remote FPGA Laboratory. 343-344
  
• David Castells-Rufas, Jordi Carrabina:
  Jumble: A Hardware-in-the-Loop Simulation System for JHDL. 345-348
  
• Junqing Sun, Gregory D. Peterson, Olaf O. Storaasli:
  Sparse Matrix-Vector Multiplication Design on FPGAs. 349-352
  
• Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood:
  Changing Output Quality for Thermal Management. 353-354
  
• Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns:
  Hardware/Software co-design of a key point detector on FPGA. 355-356
  

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