19. FCCM 2011:
Salt Lake City, Utah, USA
Paul Chow, Michael J. Wirthlin (Eds.):
IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011.
IEEE Computer Society 2011
Reconfigurable Computing
- Krishna K. Nagar, Jason D. Bakos:
A Sparse Matrix Personality for the Convey HC-1.
1-8

- Lingkan Gong, Oliver Diessel:
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification.
9-16

- Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong:
Mixed Precision Processing in Reconfigurable Systems.
17-24

- Robin Panda, Scott Hauck:
Dynamic Communication in a Coarse Grained Reconfigurable Array.
25-28

- Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker:
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.
29-32

- Jainik Kathiara, Miriam Leeser:
An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs.
33-36

- Zheng Ding, Feng Zhao, Tinghui Wang, Wei Shu, Min-You Wu:
Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board.
37-40

Comparing Implementations of Applications on Different Architectures
- Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan:
An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.
41-48

- Jian Li, Marinko Sarunic, Lesley Shannon:
Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUs.
49-56

- Matina Lakka, Grigorios Chrysos, Ioannis Papaefstathiou, Apostolos Dollas:
Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU.
57-64

- Kostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos:
Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors.
65-68

Applications I
- Peter Lieber, Brad L. Hutchings:
FPGA Communication Framework.
69-72

- Matt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt:
Efficient Calculation of Pairwise Nonbonded Forces.
73-76

- Yi-Hua Edward Yang, Oguzhan Erdem, Viktor K. Prasanna:
High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search.
77-80

- Sascha Mühlbach, Andreas Koch:
A Scalable Multi-FPGA Platform for Complex Networking Applications.
81-84

- Liu Ling, Jincan Zhuang, Qianying Zhu, Shunyu Zhu, Zhiyuan Zhang, Xinxin Zhang, Lu Cao, Zhihong Yu, Xiangbin Wu, Dong Liu:
An FPGA-Based Optical IOH Architecture for Embedded System.
85-88

- Qiwei Jin, Wayne Luk, David B. Thomas:
On Comparing Financial Option Price Solvers on FPGA.
89-92

- Robin Pottathuparambil, Jack Coyne, Jeffrey Allred, William Lynch, Vincent Natoli:
Low-Latency FPGA Based Financial Data Feed Handler.
93-96

- Janarbek Matai, Ali Irturk, Ryan Kastner:
Design and Implementation of an FPGA-Based Real-Time Face Recognition System.
97-100

- Yu Cai, Erich F. Haratsch, Mark McCartney, Ken Mai:
FPGA-Based Solid-State Drive Prototyping Platform.
101-104

- Zhong-Ho Chen, Alvin Wen-Yu Su, Ming-Ting Sun, Scott Hauck:
Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis Tool.
105-108

- Kunjan Patel, Séamas McGettrick, Chris J. Bleakley:
SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing.
109-112

- Bharat Sukhwani, Bülent Abali, Bernard Brezzo, Sameh W. Asaad:
High-Throughput, Lossless Data Compresion on FPGAs.
113-116

Tools
- Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping.
117-124

- Sebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert, Marco D. Santambrogio:
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.
125-132

- Andy Gill, Tristan Bull, Daniel DePardo, Andrew Farmer, Ed Komp, Erik Perrins:
Using Functional Programming to Generate an LDPC Forward Error Corrector.
133-140

Reconfigurable Computing in the Cloud
Architecture and Systems
- Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.
146-153

- Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French:
The PowerPC 405 Memory Sentinel and Injection System.
154-161

- Andrew G. Schmidt, Bin Huang, Ron Sass, Matthew French:
Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs.
162-169

- Aws Ismail, Lesley Shannon:
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators.
170-177

High-Level Synthesis
- Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong:
Multilevel Granularity Parallelism Synthesis on FPGAs.
178-185

- Muhsen Owaida, Nikolaos Bellas, Konstantis Daloukas, Christos D. Antonopoulos:
Synthesis of Platform Architectures from OpenCL Programs.
186-193

- Zain-ul-Abdin, Anders Ahlander, Bertil Svensson:
Programming Real-Time Autofocus on a Massively Parallel Reconfigurable Architecture Using Occam-pi.
194-201

- Davor Capalija, Tarek S. Abdelrahman:
Towards Synthesis-Free JIT Compilation to Commodity FPGAs.
202-205

- Suraj Gowda, Aaron Parsons, Robert Jarnot, Dan Werthimer:
Automated Placement for Parallelized FPGA FFTs.
206-209

- Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson:
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.
210-213

- Rohit Sinha, Hiren D. Patel:
Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis.
214-217

Applications II
Posters
- Emilio Castillo, Javier Castillo, Javier Cano, Pablo Huerta, José Ignacio Martínez:
A Key Size Configurable High Speed RSA Coprocessor.
250

- Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Peak Matrix Performance on FPGAs.
251

- Ming Yan, Ziyu Yang, Sikun Li, Liu Yang:
Reconsideration of Computing Paradigms and a Novel Reconfigurable Architecture.
252

- Oguzhan Erdem, Hoang Le, Viktor K. Prasanna, Cüneyt F. Bazlamaçci:
Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs.
253

- Will X. Y. Li, Ray C. C. Cheung, Wei Zhang, Rosa H. M. Chan, Dong Song, Theodore W. Berger:
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities.
254

- Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis, Konstantinos Krommydas, G. Tsoumblekas:
Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore Processors.
255

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