20. FCCM 2012: Toronto, Ontario, Canada

Architecture

• Oriol Arcas, Philipp Kirchhofer, Nehir Sönmez, Martin Schindewolf, Osman S. Unsal, Wolfgang Karl, Adrián Cristal:
  A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory. 1-8
  
• Srinidhi Kestur, John D. Davis, Eric S. Chung:
  Towards a Universal FPGA Matrix-Vector Multiplication Architecture. 9-16
  
• Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
  Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. 17-24
  
• Manish Kumar Jaiswal, Ray C. C. Cheung:
  Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. 25-28
  
• Eduardo Gudis, Gooitzen van der Wal, Sujit Kuthirummal, Sek Chai:
  Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA. 29-32
  
• Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong:
  A Mixed Precision Methodology for Mathematical Optimisation. 33-36
  

Reconfiguration

• Christian Beckhoff, Dirk Koch, Jim Torresen:
  Go Ahead: A Partial Reconfiguration Framework. 37-44
  
• Christopher Dennl, Daniel Ziener, Jürgen Teich:
  On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. 45-52
  
• Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
  Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. 53-60
  
• Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitris S. Nikolopoulos:
  Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. 61-64
  
• Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda:
  Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. 65-68
  

Applications 1

• Xiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid:
  FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP. 69-76
  
• Hélène Martorell, Nachiket Kapre:
  FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++. 77-84
  
• Mihalis Psarakis, Aggelos Pikrakis, Giannis Dendrinos:
  FPGA-based Acceleration for Tracking Audio Effects in Movies. 85-92
  
• Alexander Brant, Guy G. F. Lemieux:
  ZUMA: An Open FPGA Overlay Architecture. 93-96
  
• Jing Yan, Zhanxiang Zhao, Ning-Yi Xu, Xi Jin, Lin-Tao Zhang, Feng-Hsiung Hsu:
  Efficient Query Processing for Web Search Engine with FPGAs. 97-100
  

Power and Measurement

• Moritz Schmid, Frank Hannig, Jürgen Teich:
  Power Management Strategies for Serial RapidIO Endpoints in FPGAs. 101-108
  
• Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
  Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. 109-116
  
• Yamuna Rajasekhar, Rahul R. Sharma, Ron Sass:
  An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems. 117-120
  
• Rémi Busseuil, Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Michel Robert:
  Remote Execution in Distributed Memory MPSoC. 121-124
  

Applications 2

• Isaac Liu, Edward A. Lee, Matthew Viele, Guoqiang Wang, Hugo A. Andrade:
  A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs. 125-132
  
• Simon W. Moore, Paul J. Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar:
  Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. 133-140
  
• Srinidhi Kestur, Sun-Mi Park, Jagdish Sabarad, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla:
  Emulating Mammalian Vision on Reconfigurable Hardware. 141-148
  
• Gabriel L. Nazar, Luigi Carro:
  Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs. 149-152
  
• Grigorios Mingas, Christos-Savvas Bouganis:
  A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling Error. 153-156
  
• Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek:
  Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. 157-160
  

Bioinfomatics

• Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo:
  Hardware Acceleration of Short Read Mapping. 161-168
  
• Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek:
  Short-Read Mapping by a Systolic Custom FPGA Computation. 169-176
  
• Atabak Mahram, Martin C. Herbordt:
  FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined Prefiltering. 177-183
  
• Wen Tang, Wendi Wang, Bo Duan, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun:
  Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator. 184-187
  
• Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe:
  Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes. 188-191
  

Compilers and Systems

• João M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk:
  Specifying Compiler Strategies for FPGA-based Systems. 192-199
  
• Pascal Cotret, Jérémie Crenne, Guy Gogniat, Jean-Philippe Diguet:
  Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative. 200-207
  
• Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel:
  PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors. 208-215
  
• Matthew Jacobsen, Yoav Freund, Ryan Kastner:
  RIFFA: A Reusable Integration Framework for FPGA Accelerators. 216-219
  
• Louis Woods, Ken Eguro:
  Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAs. 220-223
  

GPUs and Data Parallelisms

• G. Falcao, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
  Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. 224-231
  
• Brian Van Essen, Chris Macaraeg, Maya Gokhale, Ryan Prenger:
  Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA? 232-239
  

Poster Papers

• George Eichinger, Kaushik Chowdhury, Miriam Leeser:
  Cognitive Radio Universal Software Hardware. 240
  
• Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
  Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. 241
  
• Andreas Ehliar:
  EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner. 242
  
• Mary Ellen Tie, Miriam Leeser:
  Implementing Murf: Accelerating Large State Space Exploration on FPGAs. 243
  
• Joseph G. Wingbermuehle, Roger D. Chamberlain, Ron K. Cytron:
  ScalaPipe: A Streaming Application Generator. 244
  
• Aaron Severance, Guy Lemieux:
  VENICE: A Compact Vector Processor for FPGA Applications. 245
  

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