3. FMCAD 2000:
Austin, Texas, USA
David M. Russinoff
: A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor.
: Formal Verification of Floating Point Trigonometric Functions.
Gordon J. Pace
: The Semantics of Verilog Using Transition System Combinators.
: Sequential Equivalence Checking by Symbolic Simulation.
The following paper was mistakenly left out of the printed proceedings. It is available in the online version only.