7. FMCAD 2007:
Austin, Texas, USA
Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings.
IEEE Computer Society 2007
SAT-Based Methods
- Jocelyn Simmonds, Jessica Davies, Arie Gurfinkel, Marsha Chechik:
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC.
3-12

- Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah:
Improved Design Debugging Using Maximum Satisfiability.
13-19

- Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili:
Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.
20-26

- Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan J. Hu:
Boosting Verification by Automatic Tuning of Decision Procedures.
27-34

High-Level System Analysis
- Ariel Cohen, John W. O'Leary, Amir Pnueli, Mark R. Tuttle, Lenore D. Zuck:
Verifying Correctness of Transactional Memories.
37-44

- Naghmeh Ghafari, Arie Gurfinkel, Nils Klarlund, Richard J. Trefler:
Algorithmic Analysis of Piecewise FIFO Systems.
45-52

- Xiaofang Chen, Steven M. German, Ganesh Gopalakrishnan:
Transaction Based Modeling and Verification of Hardware Protocols.
53-61

- Yogesh S. Mahajan, Sharad Malik:
Automating Hazard Checking in Transaction-Level Microarchitecture Models.
62-65

Abstraction-Based Methods
Software Analysis Methods
Symbolic Trajectory Evaluation
Specification Theory
Industrial-Strength Verification
Reasoning about Physical Systems
Advanced Theorem-Proving Applications
- Julien Schmaltz:
A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware.
223-230

- Lee Pike:
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules.
231-238

- Sandip Ray, Jayanta Bhadra:
A Mechanized Refinement Framework for Analysis of Custom Memories.
239-242

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