8. FPGA 2000: Monterey, CA, USA

• Elias Ahmed, Jonathan Rose:
  The effect of LUT and cluster size on deep-submicron FPGA performance and density. 3-12
  
• Frank Heile, Andrew Leaver, Kerry Veenstra:
  Programmable memory blocks supporting content-addressable memory. 13-21
  
• Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska:
  A novel high throughput reconfigurable FPGA architecture. 22-29
  
• Adam J. Elbirt, Christof Paar:
  An FPGA implementation and performance evaluation of the Serpent block cipher. 33-40
  
• Hea Joung Kim, William H. Mangione-Smith:
  Factoring large numbers with programmable hardware. 41-48
  
• Jason Cong, Hui Huang, Xin Yuan:
  Technology mapping for k/m-macrocell based FPGAs. 51-59
  
• Alireza Kaviani, Stephen Dean Brown:
  Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. 60-66
  
• Steven J. E. Wilton:
  Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. 67-74
  
• Jason Cong, Kenneth Yan:
  Synthesis for FPGAs with embedded memory blocks. 75-82
  
• Huesung Kim, Arun K. Somani, Akhilesh Tyagi:
  A reconfigurable multi-function computing cache architecture. 85-94
  
• Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee:
  A C compiler for a processor with a reconfigurable functional unit. 95-100
  
• Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate:
  The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. 101
  
• Lorenz Huelsbergen:
  A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms. 105-115
  
• Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara:
  The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. 116-125
  
• S. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, Henk A. E. Spaanenburg:
  A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions. 126-134
  
• John W. Lockwood, Jonathan S. Turner, David E. Taylor:
  Field programmable port extender (FPX) for distributed routing and queuing. 137-144
  
• Ali M. Shankiti, Miriam Leeser:
  Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. 145-151
  
• Guy G. Lemieux, Paul Leventis, David M. Lewis:
  Generating highly-routable sparse crossbars for PLDs. 155-164
  
• Pak K. Chan, Martine D. F. Schlag:
  New parallelization and convergence results for NC: a negotiation-based FPGA router. 165-174
  
• Vaughn Betz, Jonathan Rose:
  Automatic generation of FPGA routing architectures from high-level descriptions. 175-184
  
• Vijay Lakamraju, Russell Tessier:
  Tolerating operational faults in cluster-based FPGAs. 187-194
  
• Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel:
  Power estimation approach for SRAM-based FPGAs. 195-202
  
• Alexander Marquardt, Vaughn Betz, Jonathan Rose:
  Timing-driven placement for FPGAs. 203-213
  
• Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers:
  Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). 217
  
• Hyuk-Jun Lee, Michael J. Flynn:
  Coarse-grained carry architecture for FPGA (poster abstract). 217
  
• Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh:
  Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). 217
  
• V. S. Balakrishnan, Hardy J. Pottinger, Fikret Erçal, Mukesh Agarwal:
  Design and implementation of an FPGA based processor for compressed images (poster abstract). 218
  
• Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
  Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). 218
  
• Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura:
  An FPGA-based genetic algorithm machine (poster abstract). 218
  
• Ian Brynjolfson, Zeljko Zilic:
  FPGA clock management for low power applications (poster abstract). 219
  
• F. S. Ogrenci, Aggelos K. Katsaggelos, Majid Sarrafzadeh:
  FPGA implementation and analysis of image restoration. 219
  
• Michael J. Wirthlin, Paul Graham:
  Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract). 219
  
• Piyush Jamkhandi, Amar Mukherjee, Kunal Mukherjee, Robert Franceschini:
  Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract). 220
  
• Andrés D. García, Jean-Luc Danger, Wayne P. Burleson:
  Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. 220
  
• Rob McCready, Jonathan Rose:
  Real-time, frame-rate face detection on a configurable hardware system (poster abstract). 221
  
• Gábor Szedö, Sandeep Neema, Jason Scott, Ted Bapty:
  Reconfigurable target recognition system (poster abstract). 221
  
• Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari:
  Scalable interconnect and power distribution for island-style FPGAs (poster abstract). 221
  
• Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
  Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). 222
  
• Abdelkrim Kamel Oudjida, Sabrina Titri, Mustapha Hamarlain:
  Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract). 222
  
• William Fornaciari, Vincenzo Piuri, Luigi Ripamonti:
  Virtualization of FPGA via segmentation (poster abstract). 222