18. FPGA 2010: Monterey, CA, USA

Pre-conference workshop

• Shepard Siegel, Michael J. Wirthlin:
  FPGA-2010 pre-conference workshop on open-source for FPGA. 1
  

SoC implementation

• Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang:
  Intel nehalem processor core made FPGA synthesizable. 3-12
  
• Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng:
  FPGA prototyping of an amba-based windows-compatible SoC. 13-22
  
• Jason Lee, Lesley Shannon:
  Predicting the performance of application-specific NoCs implemented on FPGAs. 23-32
  
• Zhimin Chen, Richard Neil Pittman, Alessandro Forin:
  Combining multicore and reconfigurable instruction set extensions. 33-36
  
• Jan R. Frigo, Eric Y. Raby, Sean M. Brennan, Christophe Wolinski, Charles Wagner, François Charot, Edward Rosten, Vinod Kulathumani:
  Energy efficient sensor node implementations. 37-40
  

High-level synthesis

• Charles Eric LaForest, J. Gregory Steffan:
  Efficient multi-ported memories for FPGAs. 41-50
  
• Shreesha Srinath, Katherine Compton:
  Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. 51-58
  
• Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong:
  Bit-level optimization for high-level synthesis and FPGA-based acceleration. 59-68
  
• Jirí Simsa, Satnam Singh:
  Designing hardware with dynamic memory abstraction. 69-72
  

Acceleration engines

• Mingjie Lin, Ilia A. Lebedev, John Wawrzynek:
  High-throughput bayesian computing machine with reconfigurable hardware. 73-82
  
• Yi-Hua E. Yang, Viktor K. Prasanna:
  High throughput and large capacity pipelined dynamic search tree on FPGA. 83-92
  
• Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ning-Yi Xu, Huazhong Yang:
  FPMR: MapReduce framework on FPGA. 93-102
  
• Dharmendra P. Gupta, Paul Chow:
  Acceleration of an analytical approach to collateralized debt obligation pricing. 103-106
  
• Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev:
  A 3d-audio reconfigurable processor. 107-110
  
• Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou:
  Accelerating Monte Carlo based SSTA using FPGA. 111-114
  

Reconfigurable computing systems

• Kuen Hung Tsoi, Wayne Luk:
  Axel: a heterogeneous cluster with FPGAs and GPUs. 115-124
  
• Chen Huang, Frank Vahid:
  Server-side coprocessor updating for mobile devices with FPGAs. 125-134
  
• Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton:
  Accurately evaluating application performance in simulated hybrid multi-tasking systems. 135-144
  

Panel

• Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro:
  Programming high performance signal processing systems in high level languages. 145
  

CAD tools

• Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu:
  Towards scalable placement for FPGAs. 147-156
  
• Jason Helge Anderson, Chirag Ravishankar:
  FPGA power reduction by guarded evaluation. 157-166
  
• Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz:
  A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. 167-176
  
• Gregory Lucas, Chen Dong, Deming Chen:
  Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. 177-180
  
• Alan Mishchenko, Robert K. Brayton, Stephen Jang:
  Global delay optimization using structural choices. 181-184
  
• Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
  Building a faster boolean matcher using bloom filter. 185-188
  

High-performance applications

• Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici:
  Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. 189-198
  
• Zefu Dai, Nick Ni, Jianwen Zhu:
  A 1 cycle-per-byte XML parsing accelerator. 199-208
  
• Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu:
  A modular NFA architecture for regular expression matching. 209-218
  
• Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier:
  Scalable network virtualization using FPGAs. 219-228
  

Reliability

• Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
  Degradation in FPGAs: measurement and modelling. 229-238
  
• Kenneth M. Zick, John P. Hayes:
  On-line sensing for healthier FPGA systems. 239-248
  
• Jonathan M. Johnson, Michael J. Wirthlin:
  Voter insertion algorithms for FPGA designs using triple modular redundancy. 249-258
  
• David L. Foster, Darrin M. Hanna:
  Maximizing area-constrained partial fault tolerance in reconfigurable logic. 259-262
  

Architecture

• Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
  The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). 263-272
  
• Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
  Efficient FPGAs using nanoelectromechanical relays. 273-282
  

Poster session 1: applications

• Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu:
  A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). 283
  
• Marc-André Daigneault, Jean-Pierre David:
  Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). 283
  
• Marcus Dutton, David C. Keezer:
  An architecture for graphics processing in an FPGA (abstract only). 283
  
• Sunwoo Kim, Won W. Ro:
  FPGA implementation of highly parallelized decoder logic for network coding (abstract only). 284
  
• Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song:
  Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only). 284
  
• Rahul Bhattachrya, Santosh Biswas, Siddhartha Mukhopadhyay:
  FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). 284
  
• Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu:
  LambdaRank acceleration for relevance ranking in web search engines (abstract only). 285
  
• Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna:
  Memory efficient string matching: a modular approach on FPGAs (abstract only). 285
  
• Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh:
  Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). 285
  

Poster session 2: high-level abstractions & CAD tools

• Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker:
  A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). 286
  
• Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell:
  A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). 286
  
• Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain:
  Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only). 286
  
• Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin:
  Reconfigurable custom floating-point instructions (abstract only). 287
  
• Y. Hamid, Martin Langhammer:
  Multiplier architectures for FPGA double precision functions (abstract only). 287
  
• Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt:
  Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). 287
  
• Peter A. Jamieson, Kenneth B. Kent:
  Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). 288
  
• Jason Cong, Kirill Minkovich:
  LUT-based FPGA technology mapping for reliability (abstract only). 288
  
• Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:
  Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). 288
  
• Taiga Takata, Yusuke Matsunaga:
  A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). 289
  

Poster session 3: architecture & design studies

• Husain Parvez, Zied Marrakchi, Habib Mehrez:
  Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). 290
  
• Mingjie Lin, Yaling Ma:
  Scalable architecture for programmable quantum gate array (abstract only). 290
  
• Julien Lamoureux, Scott Miller, Mihai Sima:
  Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only). 290
  
• Yangyang Pan, Tong Zhang:
  DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). 290
  
• Mohammed Y. Niamat, Sowmya Panuganti, Tejas Raviraj:
  Modeling and simulation of nano quantum FPGAs (abstract only). 291
  
• Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris:
  Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only). 291
  
• Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita:
  High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). 291
  
• Mike Brugge, Mohammed A. S. Khalid:
  Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). 292
  
• Shaoshan Liu, Richard Neil Pittman, Alessandro Forin:
  Energy reduction with run-time partial reconfiguration (abstract only). 292
  
• Shaoshan Liu, Richard Neil Pittman, Alessandro Forin:
  Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only). 292
  
• Donglai Dai, Aniruddha Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi:
  FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only). 293
  

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