11. FPL 2001: Belfast, Northern Ireland, UK

Invited Keynote 1

• Michael J. Flynn, Albert A. Liddicoat:
  Technology Trends and Adaptive Computing. 1-5
  

Architectural Frameworks

• Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek:
  Prototyping Framework for Reconfigurable Processors. 6-16
  
• Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling:
  An Emulator for Exploring RaPiD Configurable Computing Architectures. 17-26
  

Place and Route 1

• Joerg Abke, Erich Barke:
  A New Placement Method for Direct Mapping into LUT-Based FPGAs. 27-36
  
• PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
  fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. 37-47
  

Architecture

• Ernie Lin, Steven J. E. Wilton:
  Macrocell Architectures for Product Term Embedded Memory Arrays. 48-58
  
• Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald:
  Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. 59-69
  
• Amit Kasat, Iyad Ouaiss, Ranga Vemuri:
  Memory Synthesis for FPGA-Based Reconfigurable Computers. 70-80
  

DSP 1

• Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell:
  Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic. 81-90
  
• Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony Fagan:
  Implementation of (Normalised) RLS Lattice on Virtex. 91-100
  
• Abbes Amira, Ahmed Bouridane, Peter Milligan:
  Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing. 101-111
  

Synthesis

• Srihari Cadambi, Seth Copen Goldstein:
  Static Profile-Driven Compilation for FPGAs. 112-122
  
• Michael J. Wirthlin, Brad L. Hutchings, Carl Worth:
  Synthesizing RTL Hardware from Java Byte Codes. 123-132
  
• Klaus Harbich, Erich Barke:
  PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. 133-141
  

Encryption

• Tom Kean:
  Secure Configuration of Field Programmable Gate Arrays. 142-151
  
• Máire McLoone, John V. McCanny:
  Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. 152-161
  
• Scott McMillan, Cameron Patterson:
  JBits^TM Implementations of the Advanced Encryption Standard (Rijndael). 162-171
  

Runtime Reconfiguration 1

• Markus Weinhardt, Wayne Luk:
  Task-Parallel Programming of Reconfigurable Systems. 172-181
  
• Gordon J. Brebner, Oliver Diessel:
  Chip-Based Reconfigurable Task Management. 182-191
  
• Suraj Sudhir, Suman Nath, Seth Copen Goldstein:
  Configuration Caching and Swapping. 192-202
  

Graphics and Vision

• Miguel Arias-Estrada, Juan M. Xicotencatl:
  Multiple Stereo Matching Using an Extended Architecture. 203-212
  
• Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera:
  Implementation of a NURBS to Bézier Conversor with Constant Latency. 213-222
  
• Sergio A. Cuenca, Francisco Ibarra, Rafael Álvarez:
  Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems. 223-231
  

Invited Keynote 2

• Jeff Lawrence:
  Processing Models for the Next Generation Network [Abstract]. 232
  

Place and Route 2

• PariVallal Kannan, Dinesh Bhatia:
  Tightly Integrated Placement and Routing for FPGAs. 233-242
  
• John Karro, James P. Cohoon:
  Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays. 243-253
  

Networking

• Florian Braun, John W. Lockwood, Marcel Waldvogel:
  Reconfigurable Router Modules Using Network Protocol Wrappers. 254-263
  
• Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man:
  Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. 264-274
  

Processor Interaction

• Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana:
  The MOLEN rho-mu-Coded Processor. 275-285
  
• Marios Iliopoulos, Theodore Antonakopoulos:
  Run-Time Optimized Reconfiguration Using Instruction Forecasting. 286-295
  
• Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins:
  CRISP: A Template for Reconfigurable Instruction Set Processors. 296-305
  

Applications

• Benjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan:
  Evaluation of an FPGA Implementation of the Discrete Element Method. 306-314
  
• Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam:
  Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. 315-325
  
• Apostolos Dollas, Kyprianos Papademetriou, Nikolaos Aslanides, Tom Kean:
  A Reconfigurable Embedded Input Device for Kinetically Challenged Persons. 326-335
  

Methodology 1

• Frank Wolz, Reiner Kolla:
  Bubble Partitioning for LUT-Based Sequential Circuits. 336-345
  
• Satnam Singh, Philip James-Roxby:
  Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits. 346-356
  
• Loïc Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard Pottier:
  Placing, Routing, and Editing Virtual FPGAs. 357-366
  

DSP 2

• Lok-Kee Ting, Roger Woods, Colin Cowan:
  Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. 367-376
  
• Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano:
  A Music Synthesizer on FPGA. 377-387
  
• Shervin Sheidaei, Hamid Noori, Ahmad Akbari, Hossein Pedram:
  Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders. 388-397
  

Loops and Systolic

• Steven Derrien, Sanjay V. Rajopadhye:
  Loop Tiling for Reconfigurable Accelerators. 398-408
  
• Gilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou:
  The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. 409-419
  
• Oswaldo Cadenas, Graham M. Megson:
  A n-Bit Reconfigurable Scalar Quantiser. 420-429
  

Image Processing

• Jerzy Kasperek:
  Real Time Morphological Image Contrast Enhancement in Virtex FPGA. 430-440
  
• Albert Simpson, Jill Hunter, Moira Wylie, Yi Hu, David Mann:
  Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing. 441-450
  
• Nikolaus Voß, Bärbel Mertsching:
  Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware. 451-460
  

Invited Keynote 3

• Bill Carter:
  The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]. 461
  

Runtime Reconfiguration 2

• John MacBeth, Patrick Lysaght:
  Dynamically Reconfigurable Cores. 462-472
  
• Tim Price, Cameron Patterson:
  Reconfigurable Breakpoints for Co-debug. 473-482
  

Faults

• Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
  Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. 483-492
  
• Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
  FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. 493-502
  

Methodology 2

• Tilman Neumann, Andreas Koch:
  A Generic Library for Adaptive Computing Environments. 503-512
  
• Stephan Rühl, Peter Dillinger, Stefan Hezel, Reinhard Männer:
  Generative Development System for FPGA Processors with Active Components. 513-522
  
• João M. P. Cardoso, Horácio C. Neto:
  Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. 523-533
  
• James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer:
  System Level Tools for DSP in FPGAs. 534-543
  

Arithmetic

• Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles:
  Parameterized Function Evaluation for FPGAs. 544-554
  
• Michael J. Wirthlin, Brian McMurtrey:
  Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures. 555-564
  
• Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk:
  A Digit-Serial Structure for Reconfigurable Multipliers. 565-573
  
• Kent E. Wires, Michael J. Schulte, Don McCarley:
  FPGA Resource Reduction Through Truncated Multiplication. 574-583
  

Short Papers 1

• Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner:
  Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. 584-589
  
• Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier:
  An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars. 590-594
  
• Jim Harkin, T. Martin McGinnity, Liam P. Maguire:
  Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach. 595-600
  
• Tsutomu Maruyama, Yoshiki Yamaguchi, Atsushi Kawase:
  An Approach to Real-Time Visualization of PIV Method with FPGA. 601-606
  
• Mokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, Omar Nibouche:
  FPGA-Based Discrete Wavelet Transforms System. 607-612
  
• Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman:
  X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. 613-617
  
• Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
  Arithmetic Operation Oriented Reconfigurable Chip: RHW. 618-622
  

Short Papers 2

• Michael Dales:
  Initial Analysis of the Proteus Architecture. 623-627
  
• Eric Keller:
  Building Asynchronous Circuits with JBits. 628-632
  
• Thomas Lehmann, Andreas Schreckenberg:
  Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux. 633-637
  
• Raymond Sinnappan, Scott Hazelhurst:
  A Reconfigurable Approach to Packet Filtering. 638-642
  
• Riad Stefo, Jose Luis Nunez, Claudia Feregrino, Sudipta Mahapatra, Simon Jones:
  FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. 643-647
  
• Ram Subramanian, Santosh Pande:
  A Data Re-use Based Compiler Optimization for FPGAs. 648-652
  
• Matti Tommiska, Jorma Skyttä:
  Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware. 653-657
  
• Isidoro Urriza, José I. García-Nicolás, Alfredo Sanz, Antonio Valdovinos:
  A System on Chip for Power Line Communications According to European Home Systems Specifications. 658-662
  

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