• 
  Jürgen Becker, Marco Platzner, Serge Vernalde (Eds.): Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Springer 2004 Lecture Notes in Computer Science ISBN 3-540-22989-2

Plenary Keynotes

• 
  Wim Roelandts: FPGAs and the Era of Field Programmability. 1
• 
  Nick Tredennick, Brion Shimamoto: Reconfigurable Systems Emerge. 2-11
• 
  Mark Dickinson: System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE? 12

Organic and Biology Computing

• 
  Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue: Hardware Accelerated Novel Protein Identification. 13-22
• 
  Stefan Dydel, Piotr Bala: Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices. 23-32

Security and Cryptography 1

• 
  Jonathan Graf, Peter M. Athanas: A Key Management Architecture for Securing Off-Chip Data Transfers. 33-42
• 
  Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena: FPGA Implementation of Biometric Authentication System Based on Hand Geometry. 43-53

Platform Based Design

• 
  Tero Rissa, Peter Y. K. Cheung, Wayne Luk: SoftSONIC: A Customisable Modular Platform for Video Applications. 54-63
• 
  A. Bigot, F. Charpentier, Helena Krupnova, I. Sans: Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. 64-73

Algorithms and Architectures

• 
  Tim Kerins, Emanuel M. Popovici, William P. Marnane: Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. 74-83
• 
  François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel: Power Analysis Attacks Against FPGA Implementations of the DES. 84-94

Acceleration Application 1

• 
  Maya Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald Minnich: Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer. 95-104
• 
  Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano: Stochastic Simulation for Biochemical Reactions on FPGA. 105-114

Architecture 1

• 
  Alexander Thomas, Jürgen Becker: Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. 115-124
• 
  Frederick C. Furtek, Eugene Hogenauer, James Scheuermann: Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine. 125-134
• 
  Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. 135-144
• 
  Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: A Dual-V_DD Low Power FPGA Architecture. 145-157

Physical Design 1

• 
  Gang Chen, Jason Cong: Simultaneous Timing Driven Clustering and Placement for FPGAs. 158-167
• 
  Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng: Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. 168-178
• 
  Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma: Compact Buffered Routing Architecture. 179-188
• 
  Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu: On Optimal Irregular Switch Box Designs. 189-199

Arithmetic 1

• 
  Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. 200-208
• 
  Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps: Comparative Study of SRT-Dividers in FPGA. 209-220
• 
  Jérémie Detrey, Florent de Dinechin: Second Order Function Approximation Using a Single Multiplication on FPGAs. 221-230
• 
  Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater: Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application. 231-240

Multitasking

• 
  Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos: A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. 241-250
• 
  Sebastian Lange, Martin Middendorf: The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures. 251-260

Circuit Technology

• 
  Minoru Watanabe, Fuminori Kobayashi: A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. 261-269
• 
  Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. Ferguson: Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device. 270-278

Memory 1

• 
  Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer: Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA. 279-288
• 
  Fatih Kocan, Jason Meyer: Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. 289-300

Network Processing

• 
  David V. Schuehler, John W. Lockwood: A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks. 301-310
• 
  Zachary K. Baker, Viktor K. Prasanna: Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. 311-321

Testing

• 
  Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko: BIST Based Interconnect Fault Location for FPGAs. 322-332
• 
  Abilio Parreira, João Paulo Teixeira, Marcelino B. Santos: FPGAs BIST Evaluation. 333-343

Applications

• 
  C. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa: Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. 344-353
• 
  Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe: Evaluating Fault Emulation on FPGA. 354-363

Arithmetic 2

• 
  Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk: Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. 364-373
• 
  Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Multiple Restricted Multiplication. 374-383

Signal Processing 1

• 
  Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García: Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. 384-393
• 
  Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath: A Steerable Complex Wavelet Construction and Its Implementation on FPGA. 394-403

Computational Models and Compiler

• 
  Gordon J. Brebner: Programmable Logic Has More Computational Power than Fixed Logic. 404-413
• 
  Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner: JHDLBits: The Merging of Two Worlds. 414-423
• 
  Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh: A System Level Resource Estimation Tool for FPGAs. 424-433
• 
  Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis: The PowerPC Backend Molen Compiler. 434-443

Dynamic Reconfiguration 1

• 
  Manish Handa, Ranga Vemuri: An Integrated Online Scheduling and Placement Methodology. 444-453
• 
  Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. 454-463
• 
  Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki: Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. 464-473
• 
  Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva: Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters. 474-483

Network and Optimization Algorithms

• 
  Yutaka Sugawara, Mary Inaba, Kei Hiraki: Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems. 484-493
• 
  Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima: Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. 494-504
• 
  Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya: Three-Dimensional Dynamic Programming for Homology Search. 505-515
• 
  Shin'ichi Wakabayashi, Kenji Kikuchi: An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. 516-525

System-on-Chip 1

• 
  Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong: IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. 526-535
• 
  Mark Holland, Scott Hauck: Automatic Creation of Reconfigurable PALs/PLAs for SoC. 536-545

High Speed Design

• 
  Daniel Denning, James Irvine, Malachy Devlin: A Key Agile 17.4 Gbit/sec Camellia Implementation. 546-554
• 
  Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard: High Performance True Random Number Generator in Altera Stratix FPLDs. 555-564

Security and Cryptography 2

• 
  Norbert Pramstaller, Johannes Wolkerstorfer: A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays. 565-574
• 
  Joseph Zambreno, David Nguyen, Alok N. Choudhary: Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. 575-585

Architecture 2

• 
  Sandeep S. Kumar, Christof Paar: Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor. 586-595

Memory 2

• 
  Miljan Vuletic, Laura Pozzi, Paolo Ienne: Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. 596-605
• 
  Dalia Dagher, Iyad Ouaiss: Storage Allocation for Diverse FPGA Memory Specifications. 606-616

Image Processing 1

• 
  Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo, Rodrigo Agís: Real Time Optical Flow Processing System. 617-626
• 
  Tim Todman, Wayne Luk: Methods and Tools for High-Resolution Imaging. 627-636

Network-on-Chip

• 
  Andrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric Robert: Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. 637-647
• 
  Christophe Layer, Hans-Jörg Pfleiderer: A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. 648-657

Power Aware Design 1

• 
  Sumit Mohanty, Viktor K. Prasanna: A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems. 658-668
• 
  Jawad Khan, Ranga Vemuri: An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. 669-678

IP-Based Design

• 
  Holger Lange, Andreas Koch: HW/SW Co-design by Automatic Embedding of Complex IP Cores. 679-689
• 
  Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. 690-699
• 
  Rawat Siripokarpirom: Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. 700-709
• 
  Arthur Segard, François Verdier: SOC and RTOS: Managing IPs and Tasks Communications. 710-718

Power Aware Design 2

• 
  Steven J. E. Wilton, Su-Shin Ang, Wayne Luk: The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. 719-728
• 
  Jingzhao Ou, Viktor K. Prasanna: A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms. 729-739
• 
  Rajarshi Mukherjee, Seda Ogrenci Memik: Power-Driven Design Partitioning. 740-750
• 
  Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena: Power Consumption Reduction Through Dynamic Reconfiguration. 751-760

Coprocessing Architectures

• 
  Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner: The XPP Architecture and Its Co-simulation Within the Simulink Environment. 761-770
• 
  Muhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu: An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer. 771-780
• 
  Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek: Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. 781-790
• 
  Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller: Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment. 791-800

Embedded Tutorials

• 
  Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru: Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. 801-810
• 
  Adam Donlin, Axel Braun, Adam Rose: SystemC for the Design and Modeling of Programmable Systems. 811-820
• 
  Jim Torresen: An Evolvable Hardware Tutorial. 821-830

Dynamic Reconfiguration 2

• 
  Herbert Walder, Marco Platzner: A Runtime Environment for Reconfigurable Hardware Operating Systems. 831-835
• 
  Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri: A Dynamically Reconfigurable Asynchronous FPGA Architecture. 836-841
• 
  Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert: Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. 842-846

Physical Design 2

• 
  Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen: Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. 847-851
• 
  Alexander Danilin, Sergei Sawitzki: Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs. 852-856
• 
  Shawn Phillips, Akshay Sharma, Scott Hauck: Automating the Layout of Reconfigurable Subsystems via Template Reduction. 857-861

Acceleration Application 2

• 
  Tom Van Court, Yongfeng Gu, Martin C. Herbordt: FPGA Acceleration of Rigid Molecule Interactions. 862-867
• 
  Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. 868-873
• 
  Cristinel Ababei, Pongstorn Maidee, Kia Bazargan: Exploring Potential Benefits of 3D FPGA Integration. 874-880

System Level Design

• 
  Yang Qu, Kari Tiensyrjä, Kostas Masselos: System-Level Modeling of Dynamically Reconfigurable Co-processors. 881-885
• 
  João Canas Ferreira, José Silva Matos: A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. 886-890

Physical Interconnect

• 
  Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta: Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. 891-899
• 
  Renqiu Huang, Manish Handa, Ranga Vemuri: Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. 900-905

Computational Models

• 
  Hossam A. ElGindy, George Ferizis: Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware. 906-910
• 
  Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri: Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA. 911-916

Acceleration Applications 3

• 
  Martin Schoeberl: Java Technology in an FPGA. 917-921
• 
  Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Joel Arrais: Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. 922-926
• 
  Chrilly Donninger, Ulf Lorenz: The Chess Monster Hydra. 927-932

Arithmetic 3

• 
  Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe: FPGA-Efficient Hybrid LUT/CORDIC Architecture. 933-937
• 
  Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer: A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. 938-942
• 
  Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada: Design and Implementation of a CFAR Processor for Target Detection. 943-947

Signal Processing 2

• 
  Joseph Palmer, Brent E. Nelson: A Parallel FFT Architecture for FPGAs. 948-953
• 
  Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer: FPGA Custom DSP for ECG Signal Analysis and Compression. 954-958
• 
  Quoc Thai Ho, Daniel Massicotte: FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems. 959-964

System-on-Chip 2

• 
  Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu: Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. 965-969
• 
  Erik Schüler, Luigi Carro: A Low Power FPAA for Wide Band Applications. 970-974
• 
  Edson L. Horta, John W. Lockwood: Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. 975-979

Image Processing 2

• 
  Tsutomu Maruyama: Real-Time Computation of the Generalized Hough Transform. 980-985
• 
  Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides: Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. 986-990
• 
  Faycal Bensaali, Abbes Amira: Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic. 991-995

Cryptography and Compression

• 
  Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado: High Throughput Serpent Encryption Implementation. 996-1000
• 
  Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi: Implementation of Elliptic Curve Cryptosystems over GF(2ⁿ) in Optimal Normal Basis on a Reconfigurable Computer. 1001-1005
• 
  Hagen Gädke, Andreas Koch: Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V. 1006-1010

Network Applications and Architectures

• 
  María Dolores Valdés, Miguel A. Domínguez, María José Moure, Camilo Quintáns: A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses. 1011-1016
• 
  Philip James-Roxby, Gordon J. Brebner: Multithreading in a Hyper-programmable Platform for Networked Systems. 1017-1021
• 
  Ricardo S. Ferreira, João M. P. Cardoso, Horácio C. Neto: An Environment for Exploring Data-Driven Architectures. 1022-1026
• 
  Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber: FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. 1027-1031

Network on Chip and Adaptive Architectures

• 
  Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich: A Dynamic NoC Approach for Communication in Reconfigurable Devices. 1032-1036
• 
  Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker: Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. 1037-1041
• 
  Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato: FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. 1042-1046
• 
  N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. 1047-1051

Debugging and Test

• 
  Kris Tiri, Ingrid Verbauwhede: Secure Logic Synthesis. 1052-1056
• 
  Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo: Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. 1057-1061
• 
  Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz Chavero, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa: The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead. 1062-1066
• 
  Andrzej Krasniewski: Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. 1067-1072

Organic and Biology Computing (Poster)

• 
  Chris Clarke, Lin Qiang, Herbert Peremans, Álvaro Hernández: FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head. 1073-1075
• 
  Terrence S. T. Mak, Kai-Pui Lam: FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. 1076-1079
• 
  Albert A. Conti, Tom Van Court, Martin C. Herbordt: Processing Repetitive Sequence Structures with Mismatches at Streaming Rate. 1080-1083
• 
  Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernando Morgado Dias: Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA. 1084-1086
• 
  Enrique Cantó, Nicolau Canyellas, Mariano Fons, Francisco Fons, Mariano López: FPGA Implementation of the Ridge Line Following Fingerprint Algorithm. 1087-1089

Security and Cryptography (Poster)

• 
  Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner: A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. 1090-1092
• 
  David Nguyen, Joseph Zambreno, Gokhan Memik: Flow Monitoring in High-Speed Networks with 2D Hash Tables. 1093-1097
• 
  Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä: A VHDL Generator for Elliptic Curve Cryptography. 1098-1100
• 
  Alessandro Bogliolo, Valerio Freschi, Filippo Miglioli, Matteo Canella: FPGA-Based Parallel Comparison of Run-Length-Encoded Strings. 1101-1103
• 
  Juan Manuel García Chamizo, Andrés Fuster Guilló, Jorge Azorín López: Real Environments Image Labelling Based on Reconfigurable Architectures. 1104-1106

Mapping and Compilers (Poster)

• 
  Jan Borgosz: Object Oriented Programming Paradigms for the VHDL. 1107-1109
• 
  Ivan Gonzalez, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez: Using Reconfigurable Hardware Through Web Services in Distributed Applications. 1110-1112
• 
  Nastaran Baradaran, Joonseok Park, Pedro C. Diniz: Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. 1113-1115
• 
  K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. 1116-1118
• 
  Pierre Niang, Thierry Grandpierre, Mohamed Akil, Yves Sorel: AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits. 1119-1123

Architectures (Poster)

• 
  Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga: A Self-Reconfiguration Framework for Multiprocessor CSoPCs. 1124-1126
• 
  Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger: A Virtual File System for Dynamically Reconfigurable FPGAs. 1127-1129
• 
  Tapio Ristimäki, Jari Nurmi: Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array. 1130-1132
• 
  Tomás Marek, Martin Novotný, Ludek Crha: Design and Implementation of the Memory Scheduler for the PC-Based Router. 1133-1135

Algorithms and IP (Poster)

• 
  Eric E. Fabris, Luigi Carro, Sergio Bampi: Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. 1136-1138
• 
  Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz: Intellectual Property Protection for RNS Circuits on FPGAs. 1139-1141
• 
  René de Jesús Romero-Troncoso, Gilberto Herrera Ruiz: FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines. 1142-1145
• 
  Milos Drutarovský, Viktor Fischer: Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector. 1146-1148
• 
  Jan Schier, Antonin Hermanek: Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. 1149-1151

mage Processing (Poster)

• 
  Viorela Ila, Rafael García, François Charot, Joan Batlle: FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot. 1152-1154
• 
  Hiroaki Niitsuma, Tsutomu Maruyama: Real-Time Detection of Moving Objects. 1155-1157
• 
  Sonia Mota, Eduardo Ros, Javier Díaz, Eva M. Ortigosa, Rodrigo Agís, Richard R. Carrillo: Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs. 1158-1161
• 
  Pierre Chalimbaud, François Berry: Versatile Imaging Architecture Based on a System on Chip. 1162-1164
• 
  Constantinos Skarpathiotis, Keith R. Dimond: A Hardware Implementation of a Content Based Image Retrieval Algorithm. 1165-1167

PhD Forum (Poster)

• 
  Ali Ahmadinia: Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p. 1168
• 
  Aman Gayasen: Low Power Reconfigurable Devices. 1169
• 
  Brian F. Veale, John K. Antonio, Monte P. Tull: Code Re-ordering for a Class of Reconfigurable Microprocessors. 1170
• 
  Christian Haubelt: Design Space Exploration for Distributed Hardware Reconfigurable Systems. 1171
• 
  Cristinel Ababei: TPR: Three-D Place and Route for FPGAs. 1172
• 
  David B. Thomas, Wayne Luk: Implementing Graphics Shaders Using FPGAs. 1173
• 
  Dirk Koch: Preemptive Hardware Task Management. 1174
• 
  Graham Schelle, Dirk Grunwald: Automated Speculation and Parallelism in High Performance Network Applications. 1175
• 
  Heidi E. Ziegler: Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems. 1176-1177
• 
  Javier Resano: A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. 1178-1179
• 
  Joseph Zambreno: Design and Evaluation of an FPGA Architecture for Software Protection. 1180
• 
  Mahim Mishra: Scalable Defect Tolerance Beyond the SIA Roadmap. 1181-1182
• 
  Mohamed Taher, Tarek A. El-Ghazawi: Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems. 1183
• 
  Nalin Sidahao: Optimized Field Programmable Gate Array Based Function Evaluation. 1184
• 
  R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti: MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. 1185
• 
  Ray C. C. Cheung: A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware. 1186-1187
• 
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