• 
  Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis (Eds.): FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007. IEEE 2007 ISBN 1-4244-1060-6

Keynotes

• 
  Ajay V. Bhatt: The Intel Geneseo Project. 1
• 
  Mark Dickinson: System-Level Design for FPGAs. 2
• 
  John Wawrzynek: Adventures with a Reconfigurable Research Platform. 3
• 
  Steve Trimberger: Redefining the FPGA for the Next Generation. 4

Applications I

• 
  Gareth W. Morris, Matthew Aubury: Design Space Exploration of the European Option Benchmark Using HyperStreams. 5-10
• 
  Jahyun J. Koo, Alan C. Evans, Warren J. Gross: Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. 11-16
• 
  Fernando Pardo, P. López, Diego Cabello: Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation. 17-22

Design Tools & Compilers I

• 
  Johan Ditmar, Steve McKeever: Array Synthesis in SystemC Hardware Compilation. 23-28
• 
  Jérémie Detrey, Florent de Dinechin: Floating-Point Trigonometric Functions for FPGAs. 29-34
• 
  Karel Bruneel, Peter Bertels, Dirk Stroobandt: A Method for Fast Hardware Specialization at run-time. 35-40

Multicore Systems

• 
  Heiner Giefers, Marco Platzner: A Many-core Implementation based on the Reconfigurable Mesh Model. 41-46
• 
  Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee: An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. 47-53
• 
  Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz: RAMP Blue: A Message-Passing Manycore System in FPGAs. 54-61

Applications II

• 
  Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Bart Kincaid: A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. 62-67
• 
  Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. 68-73
• 
  S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot: Performance Modeling of 2D Cellular Automata on FPGA. 74-78

High Performance Computing

• 
  Esam El-Araby, Ivan Gonzalez, Tarek A. El-Ghazawi: Bringing High-Performance Reconfigurable Computing to Exact Computations. 79-85
• 
  Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris: Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems. 86-91
• 
  Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal: Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. 92-97

Run-Time Support I

• 
  Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews: Supporting High Level Language Semantics Within Hardware Resident Threads. 98-103
• 
  Aric D. Blumer, Henning S. Mortveit, Cameron D. Patterson: Formal Modeling of Process Migration. 104-110
• 
  John Shield, Peter Sutton, Philip Machanick: Dynamic Cache Switching in Reconfigurable Embedded Systems. 111-116

Placement & Routing I

• 
  Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings: Improving Timing-Driven FPGA Packing With Physical Information. 117-123
• 
  Julien Lamoureux, Steven J. E. Wilton: Clock-Aware Placement for FPGAs. 124-131
• 
  Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng: Fast On-line Task Placement and Scheduling on Reconfigurable Devices. 132-138

Biology Applications I

• 
  Shuichi Watanabe, Junji Kitamichi, Kenichi Kuroda: A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem. 139-144
• 
  Yoshiki Yamaguchi, Tsutomu Maruyama, Fumikazu Konishi, Akihiko Konagaya: High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences. 145-150
• 
  Josh Model, Martin C. Herbordt: Discrete Event Simulation of Molecular Dynamics with Configurable Logic. 151-158

Power I

• 
  Shilpa Bhoj, Dinesh Bhatia: Pre-route Interconnect Capacitance and Power Estimation in FPGAs. 159-164
• 
  Pao-Ann Hsiung, Chih-Wen Liu: Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems. 165-170
• 
  Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll: A Power Estimation Model for an FPGA-based Softcore Processor. 171-176

Communication & Security

• 
  Graham Schelle, Jeff Fifield, Dirk Grunwald: A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. 177-182
• 
  Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz: Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. 183-188
• 
  Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls: Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection. 189-195

Architecture I

• 
  Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. 196-201
• 
  Bradley R. Quinton, Steven J. E. Wilton: Embedded Programmable Logic Core Enhancements for System Bus Interfaces. 202-209
• 
  Martin Labrecque, J. Gregory Steffan: Improving Pipelined Soft Processors with Multithreading. 210-215

Image & Video Processing

• 
  Zdenek Vasícek, Lukás Sekanina: An area-efficient alternative to adaptive median filtering in FPGAs. 216-221
• 
  Michael Wisdom, Peter Lee: An Efficient Implementation of a 2D DWT on FPGA. 222-227
• 
  Adam Major, Ioannis Nousias, Sami Khawam, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan: H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture. 228-233

Power II

• 
  Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: On the feasibility of early routing capacitance estimation for FPGAs. 234-239
• 
  Juanjo Noguera, Irwin O. Kennedy: Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. 240-245
• 
  Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood: Adaptive Thermoregulation for Applications on Reconfigurable Devices. 246-253

Biology Applications II

• 
  Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano: FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. 254-259
• 
  Octavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian Lelutiu: GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains. 260-266
• 
  Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy: A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. 267-272

Design Tools & Compilers II

• 
  Pan Yu, Tulika Mitra: Disjoint Pattern Enumeration for Custom Instructions Identification. 273-278
• 
  Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha: Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. 279-284
• 
  Holger Lange, Andreas Koch: An Execution Model for Hardware/Software Compilation and its System-Level Realization. 285-292

Placement & Routing II

• 
  Shannon Koh, Oliver Diessel: Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. 293-298
• 
  Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara: Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. 299-304
• 
  Pongstorn Maidee, Kia Bazargan: A generalized and unified SPFD-based rewiring technique. 305-310

Architecture II

• 
  Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt: Improving External Memory Access for Avalon Systems on Programmable Chips.. 311-316
• 
  Christof Pitter, Martin Schoeberl: Time Predictable CPU and DMA Shared Memory Access. 317-322
• 
  Mahim Mishra, Seth Copen Goldstein: Virtualization on the Tartan Reconfigurable Architecture. 323-330

Design Tools & Compilers III

• 
  Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann: A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. 331-338
• 
  Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann: Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97). 339-344
• 
  Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung: Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. 345-350

Placement & Routing III

• 
  Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker: Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. 351-356
• 
  John A. Nestor, Jeremy Lavine: L4: An FPGA-Based Accelerator for Detailed Maze Routing. 357-362
• 
  Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen: Improving Annealing Via Directed Moves. 363-370

Networks on Chip

• 
  Christian Schuck, Stefan Lamparth, Jürgen Becker: artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. 371-376
• 
  Martin Schoeberl: A Time-Triggered Network-on-Chip. 377-382
• 
  Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. 383-388
• 
  Mário P. Véstias, Horácio C. Neto: Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. 389-394

EU Session

• 
  Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez: The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. 396-401
• 
  Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis: HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. 402-408
• 
  Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker: MORPHEUS: Heterogeneous Reconfigurable Computing. 409-414
• 
  Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat: On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. 415-422

Design Tools & Compilers IV

• 
  Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam: Equivalence Verification of FPGA and Structured ASIC Implementations. 423-428
• 
  Satish Sivaswamy, Kia Bazargan: Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. 429-434
• 
  Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu: Fault Models and Yield Analysis for QCA-based PLAs. 435-440

Run-Time Support II

• 
  Enno Lübbers, Marco Platzner: ReconOS: An RTOS supporting Hard- and Software Threads. 441-446
• 
  Wei Han, Ioannis Nousias, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan: The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures. 447-452
• 
  Panagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold, Mayuresh V. Kothare: Monte Carlo Logarithmic Number System for Model Predictive Control. 453-458

Poster Session 1

• 
  José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler: Dynamic Voltage Scaling in a FPGA-based System-on-Chip. 459-462
• 
  Martijn T. Bennebroek, Alexander Danilin: Multiplexer-based routing fabric for reconfigurable logic. 463-466
• 
  Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker: H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. 467-471
• 
  Roberto Gutierrez, Javier Valls: Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. 472-475
• 
  Andrew Morton, Jeffrey Liu, Insop Song: Efficient Priority-Queue Data Structure for Hardware Implementation. 476-479
• 
  Ralf Laue, Oliver Kelm, Sebastian Schipp, Abdulhadi Shoufan, Sorin A. Huss: Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation. 480-484
• 
  Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López: Design of a hardware accelerator for fingerprint alignment. 485-488
• 
  Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya: An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. 489-492
• 
  Kenji Kanazawa, Tsutomu Maruyama: An FPGA Solver for Very Large SAT Problems. 493-496
• 
  Ioannis Nousias, Sami Khawam, Mark Milward, Mark Muir, Tughrul Arslan: A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays. 497-500

Poster Session 2

• 
  Ricardo Menotti, Eduardo Marques, João M. P. Cardoso: Aggressive Loop Pipelining for Reconfigurable Architectures. 501-502
• 
  Hagen Gädke, Andreas Koch: Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. 503-504
• 
  Thomas Panhofer, Martin Delvai: Self-Healing Circuits for Space-Applications. 505-506
• 
  Proshanta Saha: Automatic Software Hardware Co-Design for Reconfigurable Computing Systems. 507-508
• 
  Chi Wai Yu: VPH - A Tool for Exploring Hybrid FPGAs. 509-510
• 
  Jim Stevens: Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C. 511-512
• 
  Peter M. Athanas, J. Bowen, T. Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf: Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. 513-516
• 
  Ashutosh Pal, M. Balakrishnan: A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. 517-520
• 
  Micha Nelissen, Kees van Berkel, Sergei Sawitzki: Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. 521-524
• 
  Alberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio: An Automatic Compilation Framework for Configurable Architectures. 525-528
• 
  Vinay Sriram, David Kearney: A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm. 529-532
• 
  Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid: Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. 533-536

Poster Session 3

• 
  Stamatis Vassiliadis, Filipa Duarte, Stephan Wong: A Load/Store Unit for a Memcpy Hardware Accelerator. 537-541
• 
  Jan Torben Weinkopf, Klaus Harbich, Erich Barke: Incremental Fault Emulation. 542-545
• 
  Graeme Stewart, David Renshaw, Martyn Riley: A novel motion estimation power reduction technique. 546-549
• 
  Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi: A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. 550-553
• 
  Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka: A High Speed License Plate Recognition System on an FPGA. 554-557
• 
  A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. 558-561
• 
  Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit: Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. 562-566
• 
  José M. Claver, P. Agustí, Germán León, Manel Canseco: A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA. 567-570
• 
  Rob Beun, Irek Karkowski, Maarten Ditzel: C++ based design flow for reconfigurable image processing systems. 571-575
• 
  Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A floating-point Extended Kalman Filter implementation for autonomous mobile robots. 576-579
• 
  Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. 580-584
• 
  Aric D. Blumer, Cameron D. Patterson: Hardware/Software Process Migration and RTL Simulation. 585-588
• 
  Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell: Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. 589-592

Poster Session 4

• 
  Kester Clegg, Susan Stepney, Tim Clarke: Evolutionary Search Applied to Reconfigurable Analogue Control. 593-596
• 
  Gaye Lightbody, Roger Woods, Jonathan Francey: Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. 597-600
• 
  Andrew G. Schmidt, Ron Sass: Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores. 601-604
• 
  Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser: A Design Flow to Map Parallel Applications onto FPGAs. 605-608
• 
  Irfan Syed, John A. Williams, Neil W. Bergmann: A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications. 609-612
• 
  Love Singhal, Elaheh Bozorgzadeh: Novel Multi-Layer floorplanning for Heterogeneous FPGAs. 613-616
• 
  William G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer: Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. 617-620
• 
  Jiri Kadlec, Roman Bartosinski, Martin Danek: Accelerating Microblaze Floating Point Operations. 621-624
• 
  John Shield, Peter Sutton, Philip Machanick: Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration. 625-628
• 
  José M. Claver, Germán León: High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs. 629-632
• 
  Sven-Ole Voigt, Thomas Teufel: Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms. 633-637
• 
  Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel: RIC Fast Adder and its Set Tolerant Implementation in FPGAs. 638-641

Poster Session 5

• 
  Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater: Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --. 642-647
• 
  Tomas Dedek, Tomas Marek, Tomás Martínek: High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA. 648-651
• 
  Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris: Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. 652-655
• 
  Pavel Zemcík, Martin Zádník: AdaBoost Engine. 656-660
• 
  Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic: An FPGA Based Memory Efficient Shared Buffer Implementation. 661-664
• 
  Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley: Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. 665-669
• 
  Tamer Güdü: A New Scalable Hardware Architecture for RSA Algorithm. 670-674
• 
  Irwin O. Kennedy: Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive. 675-678
• 
  Stefan Raaijmakers, Stephan Wong: Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. 679-683
• 
  Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Juan Carlos López: Dynamic reconfiguration management based on a distributed object model. 684-687
• 
  Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach: Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. 688-691
• 
  Bas Breijer, Filipa Duarte, Stephan Wong: An OCM based shared Memory controller for Virtex 4. 692-696
• 
  Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu, Stamatis Vassiliadis: DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. 697-701
• 
  Antonio Jimeno-Morenilla, Antonio Martínez, Sergio Cuenca, José-Luis Sánchez-Romero: Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining.. 702-705

Poster Session 6

• 
  Diego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo: Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. 706-709
• 
  Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns: SoPC architecture for a Key Point Detector. 710-713
• 
  Dang Ba Khac Trieu, Tsutomu Maruyama: A Pipeline Implementation of a Watershed Algorithm on FPGA. 714-717
• 
  Ernest Jamro, Kazimierz Wiatr, Maciej Wielgosz: FPGA Implementation of 64-bit Exponential Function for HPC. 718-721
• 
  Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker: A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. 722-725
• 
  Miguel Ribeiro, Leonel Sousa: A Run-time Reconfigurable Processor for Video Motion Estimation. 726-729
• 
  Yvan Eustache, Jean-Philippe Diguet: Confiuartion Management in the Context of Self Adapative Systems. 730-734
• 
  Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis: A Quantitative Prediction Model for Hardware/Software Partitioning. 735-739
• 
  Florian Dittmann, Stefan Frank: Caching in Real-time Reconfiguration Port Scheduling. 740-744
• 
  Kristopher D. Peterson, Justin L. Tripp: Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler. 745-748
• 
  Audip Pandit, Ali Akoglu: Wirelength Prediction for FPGAs. 749-752
• 
  Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber: CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs. 753-756

Poster Session 7

• 
  Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan: System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. 757-760
• 
  Gerald Hempel, Christian Hochberger: A resource optimized SoC Kit for FPGAs. 761-764
• 
  Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain: A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP. 765-769
• 
  F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martínez-Álvarez, Juan Martínez-Alajarín, Ramón Ruiz Merino: Compression system for the phonocardiographic signal. 770-773
• 
  Zdenek Pohl, Milan Tichý: RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. 774-777
• 
  Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat: NoC Implementation in FPGA Using Torus Topology. 778-781
• 
  Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir: Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors. 782-785
• 
  David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty: FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory. 786-791
• 
  Karthick Parashar, Nitin Chandrachoodan: A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. 792-795
• 
  Yohei Hasegawa, Hideharu Amano: Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. 796-799
• 
  Andreas Ehliar, Dake Liu: An fpga based open source network-on-chip architecture. 800-803
• 
  Martin Kosek, Jan Korenek: FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing. 804-807
• 
  Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. 808-811