FPT 2005:
Singagore
Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong (Eds.):
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singagore.
IEEE 2005, ISBN 0-7803-9407-0 
Arithmetic
Reconfiguration Mechanisms
Custom Computing
FPGA Applications
Configurable Architectures
Security
Physical Technology
Reconfigurable Applications
- Irwin Kennedy:
A Dynamically Reconfigured UMTS Multi-Channel Complex Code Matched Filter.
199-206
- Esam El-Araby, Mohamed Taher, Tarek A. El-Ghazawi, Jacqueline Le Moigne:
Prototyping Automatic Cloud Cover Assessment (ACCA) Algorithm for Remote Sensing On-Board Processing on a Reconfigurable Computer.
207-214
- Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk:
Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.
215-222
Tools
Biological Modelling
Poster Session 1
- Yi Lu, Neil W. Bergmann:
Dynamic Loading of Peripherals on Reconfigurable System-on-Chip.
279-280
- Timothy F. Oliver, Douglas L. Maskell:
An FPGA Model for Developing Dynamic Circuit Computing.
281-282
- Andrew Bainbridge-Smith, Su-Hyun Park:
ADH: An Aspect Described Hardware Programming Language.
283-284
- Wolfgang Klingauf, Robert Günzel:
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling.
285-286
- Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi:
Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers.
287-288
- Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio López-Buedo:
Hardware-Accelerated SSH on Self-Reconfigurable Systems.
289-290
- Arvind Sudarsanam, Aravind Dasu:
A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations.
291-292
- Sebastian Lange, Martin Middendorf:
Heuristics for Context-Caches in 2-Level Reconfigurable Architectures.
293-294
- John Harkins, Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang:
Performance of Sorting Algorithms on the SRC 6 Reconfigurable Computer.
295-296
- Minoru Watanabe, Fuminori Kobayashi:
A Zero-Overhead Dynamic Optically Reconfigurable Gate Array.
297-298
Poster Session 2
- Joshua Fender, Jonathan Rose, David R. Galloway:
The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth.
301-302
- Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni:
High Performance Channel Model Hardware Emulator for 802.11n.
303-304
- Feng Lin, Haili Wang, Jinian Bian:
HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design.
305-306
- Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour:
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms.
307-308
- Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary Fields.
309-310
- Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj:
A System-Level Design Methodology for Reconfigurable Computing Applications.
311-312
- Mihail Petrov, Manfred Glesner:
Optimal FFT Architecture Selection for OFDM Receivers on FPGA.
313-314
- Patrick Dickinson, Kofi Appiah, Andrew Hunter, Stephen Ormston:
An FPGA-Based Infant Monitoring System.
315-316
- Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor:
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator.
317-318
- Scott Fischaber, R. Hasson, John McAllister, Roger Woods:
FPGA Core Network Implementation and Optimization: A Case Study.
319-320
Poster Session 3
- Mihail Petrov, Manfred Glesner:
A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA.
323-324
- Gerd Van den Branden, Abdellah Touhafi, Erik F. Dirkx:
A Design Methodology to Generate Dynamically Self-Reconfigurable SoCs for Virtex-II Pro FPGAs.
325-326
- Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi:
Implementation of Gabor-Type Filters on Field Programmable Gate Arrays.
327-328
- Panan Potipantong, Theerayod Wiangtong, Phaophak Sirisuk, Apisak Worapishet:
A Scaleable FFT/IFFT Kernel for Communication Systems Using Codesign Approach.
329-330
- Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman:
FPGA Based Router for Cognitive Packet Networks.
331-332
- Andreas Fidjeland, Wayne Luk:
An Overview of High-Level Synthesis of Multiprocessors for Logic Programming.
333-334
- Milind M. Parelkar, Kris Gaj:
Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and Authentication.
335-336
- Siobhán Launders, Wesley Cooper, Brian Foley:
Net Power Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.
337-338
- Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
The Design of Scalable Stochastic Biochemical Simulator on FPGA.
339-340
- Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface.
341-342
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