6. Great Lakes Symposium on VLSI 1996: Ames, IA, USA

6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA. IEEE Computer Society 1996

High-level Synthesis and Special Purpose Architecture I

Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi:
Loop-List Scheduling for Heterogeneous Functional Units. 2-7
Duen-Jeng Wang, Yu Hen Hu:
Synthesis of Real-Time Recursive DSP Algorithms Using Multiple Chips. 8-13
Jian-Feng Shi, Liang-Fang Chao:
Resource-Constrained Algebraic Transformation for Loop Pipelining. 14-17
Gary William Grewal:
A Global Mode Instruction Minimization Technique for Embedded DSPs. 18-

Philippe Royannez, Amara Amara:
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. 24-28
Nalini K. Ratha, Anil K. Jain, Diane T. Rover:
FPGA-based high performance page layout segmentation. 29-34
Pong P. Chu:
A Reprogrammable FPGA-Based ATM Traffic Generator. 35-38
Kevin A. Kwiat, Warren Debany, Salim Hariri:
Software Fault Tolerance Using Dynamically Reconfigurable FPGAs. 39-

Moazzem Hossain, Bala Thumma, Sunil Ashtaputre:
A New Faster Algorithm for Iterative Placement Improvement. 44-49
Dirk Stroobandt, Herwig Van Marck, Jan Van Campenhout:
An Accurate Interconnection Length Estimation for Computer Logic. 50-55
Dinesh P. Mehta, Naveed A. Sherwani:
A Minimum-Area Floorplanning Algorithm for MBC Designs. 56-59
Jianjian Song, Heng Kek Choo, Wenjun Zhuang:
A New Model for General Connectivity and its Application to Placement. 60-

Nelson L. Passos, Edwin Hsing-Mean Sha:
A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization. 66-71
Paul Shipley, Sherif Sayed, Magdy A. Bayoumi:
A High Speed VLSI Architecture for Scaleable ATM Switches. 72-76
Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus:
A Design Exploration Environment. 77-80
Mariana-Eugenia Petre, Guido Masera:
A Parametrical Architecture for Reed-Solomon Decoders. 81-

Joseph L. Ganley, James P. Cohoon:
A Provably Good Moat Routing Algorithm. 86-85
Anthony D. Johnson:
On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing. 92-95
James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald:
Chip Pad Migration is a Key Component to High Performance MCM Design. 96-99
Jin-Tai Yan:
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. 100-

Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin:
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. 106-111
Valeria Bertacco, Maurizio Damiani:
Boolean Function Representation Using Parallel-Access Diagrams. 112-117
Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Logic Synthesis for Testability. 118-121
Seokjin Kim, Ramalingam Sridhar:
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. 122-125
Laura Heinrich-Litan, Paul Molitor, Dirk Möller:
Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs. 126-

Dongsheng Wang, Ernest S. Kuh:
Performance-Driven Interconnect Global Routing. 132-136
Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Recent Developments in Performance Driven Steiner Routing: An Overview. 137-142
Masato Edahiro, Richard J. Lipton:
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. 143-147
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Simultaneous Routing and Buffer Insertion for High Performance Interconnect. 148-153
Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
Timing and Power Optimization by Gate Sizing Considering False Paths. 154-

Enrico Macii, Massimo Poncino:
Exact Computation of the Entropy of a Logic Circuit. 162-167
Christophe Tretz, Charles A. Zukowski:
CMOS Transistor Sizing for Minimization of Energy-Delay Product. 168-173
Emad N. Farag, Mohamed I. Elmasry:
Low-Power Implementation of Discrete Cosine Transform. 174-177
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin:
Some Issues in Gray Code Addressing. 178-181
Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu:
A Hierarchal Approach for Power Reduction in VLSI Chips. 182-

Winfried Nöth, Uwe Hinsberger, Reiner Kolla:
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping. 188-193
Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
Transistor Chaining in CMOS Leaf Cells of Planar Topology. 194-199
Mario A. Lopez, Dinesh P. Mehta:
Partitioning Algorithms for Corner Stitching. 200-

Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. 208-213
Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits. 214-219
Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar:
Efficient Delay Test Generation for Modular Circuits. 220-

Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture. 228-233
Chantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha:
Rapid Prototyping for Fuzzy Systems. 234-239
Hangu Yeo, Yu Hen Hu:
A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range. 240-

José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville:
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. 246-251
L. Desormeaux, Valek Szwarc, J. Lodge:
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation. 252-255
Maher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, Harry C. Gundrum:
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications. 256-259
Jai-Sop Hyun, Kwang Sub Yoon:
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. 260-

Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian:
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits. 266-271
Ayman I. Kayssi:
Macromodeling C- and RC-loaded CMOS inverters for timing analysis. 272-276
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
On Verifying the Correctness of Retimed Circuits. 277-

Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
On Double Transition Faults as a Delay Fault Model. 282-287
Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Improving Circuit Testability by Clock Control. 288-293
Zaifu Zhang, Robert D. McLeod:
An Efficient Multiple Scan Chain Testing Scheme. 294-

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