21. ACM Great Lakes Symposium on VLSI 2011: Lausanne, Switzerland

Emerging technologies

• Jinwook Jang, Wayne Burleson:
  An arbiter based on-chip droop detector system. 1-6
  
• Shruti R. Patil, David J. Lilja:
  A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions. 7-12
  
• Christopher Condrat, Priyank Kalla, Steve Blair:
  Logic synthesis for integrated optics. 13-18
  
• Kotb Jabeur, Nataliya Yakymets, Ian O'Connor, Sébastien Le Beux:
  Fine-grain reconfigurable logic cells based on double-gate CNTFETs. 19-24
  
• Mehdi Kabir, Mircea R. Stan, Stuart A. Wolf, Ryan B. Comes, Jiwei Lu:
  RAMA: a self-assembled multiferroic magnetic QCA for low power systems. 25-30
  

NoCs and routing

• Nishit Ashok Kapadia, Sudeep Pasricha:
  VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip. 31-36
  
• Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin:
  Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs. 37-42
  
• Jie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi:
  Run-time energy management of manycore systems through reconfigurable interconnects. 43-48
  
• Mehdi Alipour, Mohammad Haji Seyed Javadi, Ali Jahanian:
  Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology. 49-54
  
• Xinyu Li, Omar Hammami:
  Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip. 55-60
  

Circuit design I

• Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro:
  Efficient shift-adds design of digit-serial multiple constant multiplications. 61-66
  
• Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
  Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs. 67-72
  
• Ayantika Chatterjee, Indranil Sengupta:
  FPGA implementation of binary edwards curve usingternary representation. 73-78
  
• Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro:
  Design of low-power multiple constant multiplications using low-complexity minimum depth operations. 79-84
  
• M. Affan Zidan, Talal Bonny, Khaled N. Salama:
  High performance technique for database applicationsusing a hybrid GPU/CPU platform. 85-90
  
• Jongpil Jung, Kyungsu Kang, Chong-Min Kyung:
  Design and management of 3D-stacked NUCA cache for chip multiprocessors. 91-96
  

Low power and temperature

• Hongbin Sun, Chuanyin Liu, Nanning Zheng, Tai Min, Tong Zhang:
  Design techniques to improve the device write margin for MRAM-based cache memory. 97-102
  
• Yebin Lee, Soontae Kim:
  DRAM energy reduction by prefetching-based memory traffic clustering. 103-108
  
• Yen-Jen Chang, Tung-Chi Wu:
  A low-power TCAM design using mask-aware match-line (MAML) technique. 109-114
  
• George Kornaros, Dionisios N. Pnevmatikatos:
  Hardware-assisted dynamic power and thermal management in multi-core SoCs. 115-120
  
• Wasim Hussain, Shah M. Jahinuzzaman:
  A 7T SRAM bit-cell for low-power embedded memories. 121-126
  

Circuit design II

• Rahul Singh, Jae-Cheol Son, Ukrae Cho, Gunok Jung, Min-Su Kim, Hyoungwook Lee, Suhwan Kim:
  A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates. 127-132
  
• Basab Datta, Wayne Burleson:
  A 45.6μ² 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS. 133-138
  
• Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula:
  A new balanced 4-moduli set {2^k, 2ⁿ - 1, 2ⁿ + 1, 2ⁿ⁺¹-1} and its reverse converter design for efficient fir filter implementation. 139-144
  
• Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil:
  Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective. 145-150
  
• Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
  A design methodology for the automatic sizing of standard-cell libraries. 151-156
  

Asynchronous circuits

• Naohiro Hamada, Hiroshi Saito:
  Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation. 157-162
  
• Mario R. Casu, Stefano Colazzo, Paolo Mantovani:
  Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. 163-168
  
• James Sebastian Guido, Alexandre Yakovlev:
  Reconfigurable controllers for synchronization via wagging. 175-180
  
• Masoud Zamani, Mehdi Baradaran Tahoori:
  Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays. 181-186
  

CAD

• Chenglong Xiao, Emmanuel Casseau:
  An efficient algorithm for custom instruction enumeration. 187-192
  
• Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
  An approximation algorithm for cofactoring-based synthesis. 193-198
  
• Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
  Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. 199-204
  
• Jin-Tai Yan, Zhi-Wei Chen:
  New optimal layer assignment for bus-oriented escape routing. 205-210
  
• Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
  Acceleration of random-walk-based linear circuit analysis using importance sampling. 211-216
  

Design of specific circuits

• Gaetano Rivela, Pietro Scavini, Daniele Grasso, Antonino Calcagno, Maria Gabriella Castro, Giuseppe Di Chiara, Giuseppe Avellone, Giovanni Calí, Salvatore Scaccianoce:
  A 65 nm CMOS low power RF front-end for L1/E1 GPS/Galileo signals. 217-222
  
• Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler:
  Simulation-based equivalence checking between SystemC models at different levels of abstraction. 223-228
  
• Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
  Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips. 229-234
  
• Shohreh Sharif Mansouri, Elena Dubrova:
  A countermeasure against power analysis attacks for FSR-based stream ciphers. 235-240
  
• Fu Luo, Godi Fischer:
  Low jitter audio range PLL with ultra low power dissipation. 241-246
  

Design for variability

• Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake:
  Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. 247-252
  
• Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
  A linear programming approach for minimum NBTI vector selection. 253-258
  
• André Lange, Joachim Haase, Hendrik T. Mau:
  Fitting standard cell performance to generalized Lambda distributions. 259-264
  
• Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu:
  Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. 265-270
  
• Mahmoud Momtazpour, Mahboobeh Ghorbani, Maziar Goudarzi, Esmaeil Sanaei:
  Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization. 271-276
  

Design for reliability

• Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González:
  Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. 277-282
  
• Albert H. Chang, Hae-Seung Lee, Duane S. Boning:
  Redundancy in SAR ADCs. 283-288
  
• Basab Datta, Wayne Burleson:
  A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics. 289-294
  
• Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
  Buffering of frequent accesses for reduced cache aging. 295-300
  
• Cristiana Bolchini, Antonio Miele, Christian Pilato:
  Combined architecture and hardening techniques exploration for reliable embedded system design. 301-306
  
• Mineo Kaneko, Keisuke Inoue:
  Ordered coloring-based resource binding for datapaths with improved skew-adjustability. 307-312
  

Circuit design III

• Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras:
  Power estimation of dividers implemented in FPGAs. 313-318
  
• Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan:
  Nanometer-scale standard cell library for enhanced redundant via1 insertion rate. 319-324
  
• Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
  Circuit design of a dual-versioning L1 data cache for optimistic concurrency. 325-330
  
• Bojan Mihajlovic, Zeljko Zilic:
  Real-time address trace compression for emulated and real system-on-chip processor core debugging. 331-336
  
• Robert Fischbach, Jens Lienig, Johann Knechtel:
  Investigating modern layout representations for improved 3d design automation. 337-342
  

Poster session I

• Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg:
  Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. 343-346
  
• Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen:
  Power efficient partial product compression. 347-350
  
• Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani:
  Evaluation of FPGA routing architectures under process variation. 351-354
  
• Swathi Ramasahayam, Satyam Mandavilli:
  High resolution MASH 2-2 Sigma Delta interface for capacitive accelerometers. 355-358
  
• Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
  Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures. 359-362
  
• Markus Dietl, Puneet Sareen:
  A new low power and area efficient semi-digital PLL architecture for low bandwidth applications. 363-366
  
• Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai:
  SIAR: splitting-graph-based interactive analog router. 367-370
  
• Anh-Tuan Do, Xiaoliang Tan, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
  A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. 371-374
  
• Arne Heittmann, Tobias G. Noll:
  Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. 375-378
  
• Frank Bouwens, Jos Huisken, Harmke de Groot, Martijn Bennebroek, Anteneh A. Abbo, Octavio Santana, Jef L. van Meerbergen, Antoine Fraboulet:
  A dual-core system solution for wearable health monitors. 379-382
  

Poster session II

• Krishna C. Chillara, Jinwook Jang, Wayne P. Burleson:
  Robust signaling techniques for through silicon via bundles. 383-386
  
• Juan Núñez, Maria J. Avedillo, José M. Quintana:
  Efficient realization of RTD-CMOS logic gates. 387-390
  
• Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
  On residue removal in digital microfluidic biochips. 391-394
  
• Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
  Repeater insertion in power-managed VLSI systems. 395-398
  
• Adam C. Cabe, Mircea R. Stan:
  Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM. 399-402
  
• Luís Guerra e Silva, Luis Miguel Silveira:
  Handling intra-die variations in PSTA. 403-406
  
• Petra Färm, Elena Dubrova, Andreas Kuehlmann:
  Integrated logic synthesis using simulated annealing. 407-410
  
• Supriyo Maji, Pradip Mandal:
  A geometric programming aided knowledge based approach for analog circuit synthesis and sizing. 411-414
  
• Shi-Qun Zheng, Ing-Chao Lin, Yen-Han Lee:
  Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect. 415-418
  
• Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
  Efficient method to compute minimum decision chains of Boolean functions. 419-422
  
• Ali Ameri, Gordon W. Roberts:
  Time-mode reconstruction iir filters for ΣΔ phase modulation applications. 423-426
  

SMECY: Smart Multi-core Embedded SYstems

• François Pacull, Koen Bertels, Martin Danek, Giulio Urlini:
  SMECY: smart multi-core embedded systems. 427-428
  

Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design

• Lionel Torres, Weisheng Zhao:
  Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design. 429-430
  
• Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert:
  Design of MRAM based logic circuits and its applications. 431-436
  
• Takahiro Hanyu:
  Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. 437-438
  
• Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta:
  Enabling architectural innovations using non-volatile memory. 439-444
  
• Keizo Kinoshita:
  Challenges for non-volatile memory & logic manufacturing utilizing magnetic tunnel junction on 300 mm wafer. 445-446
  

Hardware security in VLSI

• Wayne Burleson, Yusuf Leblebici:
  Hardware security in VLSI. 447-448
  
• Farinaz Koushanfar:
  Integrated circuits metering for piracy protection and digital rights management: an overview. 449-454
  
• Ingrid Verbauwhede, Roel Maes:
  Physically unclonable functions: manufacturing variability as an unclonable device identifier. 455-460
  
• Tim Güneysu, Stefan Heyse, Christof Paar:
  The future of high-speed cryptography: new computing platforms and new ciphers. 461-466
  

Quantum devices and optical computing

• Braulio García-Cámara:
  Quantum devices and optical computing: introduction. 467-468
  
• Oriol Romero-Isart, Anika C. Panzer, J. Ignacio Cirac:
  Optically leviting dielectrics in the quantum regime. 469-470
  
• Rainer Kaltenbaek:
  Quantum information processing beyond polarization encoding. 471-472
  
• Hugues de Riedmatten:
  Solid state optical quantum memories. 473-474
  
• Solomon Assefa, William M. J. Green, Alexander Rylyakov, Clint Schow, Folker Horst, Yurii A. Vlasov:
  Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers. 475-476
  

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