1. HPCA 1995: Raleigh, North Carolina, USA

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), Raleigh, North Carolina, USA, January 22-25, 1995. IEEE Computer Society 1995, ISBN 0-8186-6445-2

Session I-A: Register Management

Peter R. Nuth, William J. Dally:
The Named-State Register File: Implementation and Performance. 4-13
Shlomo Weiss:
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. 14-21
Josep Llosa, Mateo Valero, Eduard Ayguadé:
Non-Consistent Dual Register Files to Reduce Register Pressure. 22-31

Session I-B: Interconnection Networks

Chunming Qiao, Rami G. Melhem:
Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems. 34-43
Franck Cappello, Cécile Germain:
Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network. 44-53
Anand Sivasubramaniam, Aman Singla, Umakishore Ramachandran, H. Venkateswaran:
Abstracting Network Characteristics and Locality Properties of Parallel Systems. 54-63

Session II-A: Latency Reduction Techniques

Fredrik Dahlgren, Per Stenström:
Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. 68-77
Keith I. Farkas, Norman P. Jouppi, Paul Chow:
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? 78-89
Daniel Citron, Larry Rudolph:
Creating a Wider Bus Using Caching Techniques. 90-99

Session II-B: Routing in Mesh

Ran Libeskind-Hadas, Eli Brandt:
Origin-Based Fault-Tolerant routing in the Mesh. 102-111
Jatin Upadhyay, Vara Varavithya, Prasant Mohapatra:
Efficient and Balanced Adaptive Routing in Two-Dimensional Meshes. 112-121
Chris M. Cunningham, Dimiter R. Avresky:
Fault-Tolerant Adaptive Routing for Two-Dimensional Meshes. 122-131

Session III-A: Cache Memory

André Seznec:
DASC Cache. 134-143
Kevin B. Theobald, Herbert H. J. Hum, Guang R. Gao:
A Design Frame for Hybrid Access Caches. 144-153
Olivier Temam, Nathalie Drach:
Software Assistance for Data Caches. 154-163

Session III B: Modeling and Performance Evaluation

Younes M. Boura, Chita R. Das:
Modeling Virtual Channel Flow Control in Hypercubes. 166-175
Thomas L. Sterling, Daniel Savarese, Phillip Merkey, Jeffrey P. Gardner:
An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science Application. 176-185
Kent Treiber, Jai Menon:
Simulation Study of Cached RAID5 Designs. 186-197

Session IV-A: Synchronization and Scheduling

Dhabaleswar K. Panda:
Fast Barrier Synchronization in Wormhole k-ary n-cube Networks with Multidestination Worms. 200-209
Stuart Fiske, William J. Dally:
Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. 210-221
Maged M. Michael, Michael L. Scott:
Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors. 222-231

Session IV-B: Memory Management

Karl Westerholz, Stephen Honal, Josef Plankl, Christian Hafer:
Improving Performance by Cache Driven Memory Management. 234-242
Jesung Kim, Sang Lyul Min, Sanghoon Jeon, ByoungChul Ahn, Deog-Kyoon Jeong, Chong-Sang Kim:
U-Cache: A Cost-Effective Solution to the Synonym Problem. 243-252
Sally A. McKee, William A. Wulf:
Access Ordering and Memory-Conscious Cache Utilization. 253-262

Session V-A: Cache Coherence

Craig Anderson, Jean-Loup Baer:
Two Techniques for Improving Performance on Bus-Based Multiprocessors. 264-275
Ashley Saulsbury, Tim Wilkinson, John B. Carter, Anders Landin:
An Argument for Simple COMA. 276-285
Leonidas I. Kontothanassis, Michael L. Scott:
Software Cache Coherence for Large Scale Multiprocessors. 286-295

Session V-B: Multithreaded Architecture

Ramaswamy Govindarajan, Shashank S. Nemawarkar, Phillip LeNir:
Design and Performance Evaluation of a Multithreaded Architecture. 298-307
Tetsuo Kawano, Shigeru Kusakabe, Rin-ichiro Taniguchi, Makoto Amamiya:
Fine-Grain Multi-Thread Processor Architecture for Massively Parallel Processing. 308-317
Yamin Li, Wanming Chu:
The Effects of STEF in Finely Parallel Multithreaded Processors. 318-325

Session VI-A: Special Purpose Architectures

Raghu Sastry, N. Ranganathan:
A VLSI Architecture for Computer the Tree-to-Tree Distance. 330-339
Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang:
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. 340-347
Vivek Garg, David E. Schimmel:
Architectural Support for Inter-Stream Communication in a MSIMD System. 348-357

Session VI-B: Code Optimization

Josep Torrellas, Chun Xia, Russell L. Daigle:
Optimizing Instruction Cache Performance for Operating System Intensive Workloads. 360-369
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor:
Program Balance and Its Impact on High Performance RISC Architectures. 370-379
De-Lei Lee:
Memory Access Reordering in Vector Processors. 380-389

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