11. HPCA 2005: San Francisco, CA, USA

Keynote

• Fred Weber: Trends in High-Performance Processors. 3

Processor Architecture

• Nathan Tuck, Dean M. Tullsen:
  Multithreaded Value Prediction. 5-15
  
• Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez:
  Checkpointed Early Load Retirement. 16-27
  
• Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy:
  Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. 28-39
  
• Masaaki Kondo, Hiroshi Nakamura:
  A Small, Fast and Low-Power Register File by Bit-Partitioning. 40-49
  

Temperature, Energy, and Power

• Krishnan Sundaresan, Nihar R. Mahapatra:
  Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. 51-60
  
• Pedro Chaparro, Grigorios Magklis, José González, Antonio González:
  Distributing the Frontend for Temperature Reduction. 61-70
  
• Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron:
  Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. 71-82
  
• Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg:
  Tapping ZettaRAM^TM for Low-Power Memory Systems. 83-94
  

Communication Architectures

• Paul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai:
  An Efficient Programmable 10 Gigabit Ethernet Network Interface Card. 96-107
  
• José Duato, Ian Johnson, Jose Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós:
  A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. 108-119
  
• Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal:
  Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. 120-131
  
• Jung Ho Ahn, Mattan Erez, William J. Dally:
  Scatter-Add in Data Parallel Architectures. 132-142
  

Energy and Power

• Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González:
  Software Directed Issue Queue Power Reduction. 144-153
  
• Yan Meng, Timothy Sherwood, Ryan Kastner:
  On the Limits of Leakage Power Reduction in Caches. 154-165
  
• Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley:
  Heat Stroke: Power-Density-Based Denial of Service in SMT. 166-177
  
• Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark:
  Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors. 178-189
  

Memory System Issues

• Aamer Jaleel, Bruce L. Jacob:
  Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. 191-200
  
• Erik G. Hallnor, Steven K. Reinhardt:
  A Unified Compressed Memory Hierarchy. 201-212
  
• Zhichun Zhu, Zhao Zhang:
  A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. 213-224
  
• Lawrence Spracklen, Yuan Chou, Santosh G. Abraham:
  Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications. 225-236
  

Industrial Perspectives (I)

• Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler:
  Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. 238-242
  
• Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt:
  The Soft Error Problem: An Architectural Perspective. 243-247
  
• Lawrence Spracklen, Santosh G. Abraham:
  Chip Multithreading: Opportunities and Challenges. 248-252
  
• Parthasarathy Ranganathan, Norman P. Jouppi:
  Enterprise IT Trends and Implications for Architecture Research. 253-256
  

Industrial Perspectives (II)

• H. Peter Hofstee:
  Power Efficient Processor Architecture and The Cell Processor. 258-262
  

Panel: New Opportunities for Computer Architecture Research: An Industrial Perspective

• Wen-mei W. Hwu, Sanjay J. Patel: The Future of Computer Architecture Research: An Industrial Perspective. 264

Evaluation Methodologies

• Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins:
  Characterizing and Comparing Prevailing Simulation Techniques. 266-277
  
• Jeremy Lau, Stefan Schoenmackers, Brad Calder:
  Transition Phase Classification and Prediction. 278-289
  

Software Debugging Support

• Feng Qin, Shan Lu, Yuanyuan Zhou:
  SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs. 291-302
  
• Marc L. Corliss, E. Christopher Lewis, Amir Roth:
  Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE. 303-314
  

Multiprocessors and Multithreading

• C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie:
  Unbounded Transactional Memory. 316-327
  
• Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood:
  Improving Multiple-CMP Systems Using Token Coherence. 328-339
  
• Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin:
  Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. 340-351
  
• Youtao Zhang, Lan Gao, Jun Yang, Xiangyu Zhang, Rajiv Gupta:
  SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. 352-362
  

Last update Sun May 26 02:04:05 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page