International Conference on Computer-Aided Design (ICCAD '97), 9-13 November 1997, San Jose, CA, USA. ACM and IEEE Computer Society, 1997

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  Yirng-An Chen, Randal E. Bryant: PHDD: an efficient graph representation for floating point circuit verification. 2-7
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  Christoph Scholl, Rolf Drechsler, Bernd Becker: Functional simulation using binary decision diagrams. 8-12
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  Patrick Vuillod, Luca Benini, Giovanni De Micheli: Generalized matching from theory to application. 13-20
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  Jian Li, Rajesh K. Gupta: Decomposition of timed decision tables and its use in presynthesis optimizations. 22-27
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  Chi-Hong Hwang, Allen C.-H. Wu: A predictive system shutdown method for energy saving of event-driven computation. 28-32
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  Kyosun Kim, Ramesh Karri, Miodrag Potkonjak: Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. 33-38
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  Zhanping Chen, Kaushik Roy, Tan-Li Chou: Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. 40-44
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  Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Effects of delay models on peak power estimation of VLSI sequential circuits. 45-51
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  Chuan-Yu Wang, Kaushik Roy: COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. 52-55
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  Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. 58-65
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  Ibrahim M. Elfadel, David D. Ling: A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks. 66-71
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  Tuyen V. Nguyen, Jing Li: Multipoint Padé approximation using a rational block Lanczos algorithm. 72-75
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  Valeria Bertacco, Maurizio Damiani: The disjunctive decomposition of logic functions. 78-82
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  Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita: Speeding up technology-independent timing optimization by network partitioning. 83-90
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  Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Negative thinking by incremental problem solving: application to unate covering. 91-98
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  Catherine H. Gebotys: DSP address optimization using a minimum cost circulation technique. 100-103
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  Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith: Application-driven synthesis of core-based systems. 104-107
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  Inki Hong, Miodrag Potkonjak, Ramesh Karri: Power optimization using divide-and-conquer techniques for minimization of the number of operations. 108-111
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  Mahadevamurty Nemani, Farid N. Najm: High-level area and power estimation for VLSI circuits. 114-119
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  Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. 120-125
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  Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Achievable bounds on signal transition activity. 126-129
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  Peter Feldmann, Roland W. Freund: Circuit noise evaluation by Padé approximation based model-reduction techniques. 132-138
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  Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng: Global harmony: coupled noise analysis for full-chip RC interconnect networks. 139-146
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  Anirudh Devgan: Efficient coupled noise estimation for on-chip interconnects. 147-151
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  Charles J. DeVane: Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits. 154-161
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  Jeremy R. Levitt, Kunle Olukotun: Verifying correct pipeline implementation for microprocessors. 162-169
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  Darko Kirovski, Miodrag Potkonjak: A quantitative approach to functional debugging. 170-173
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  Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton: Approximate timing analysis of combinational circuits under the XBD0 model. 176-181
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  Mukund Sivaraman, Andrzej J. Strojwas: Timing analysis based on primitive path delay fault identification. 182-189
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  Supratik Chakraborty, David L. Dill: Approximate algorithms for time separation of events. 190-194
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  Chandramouli Visweswariah: Optimization techniques for high-performance digital circuits. 198-205
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  Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli: Sequential optimisation without state space exploration. 208-215
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  Naresh Maheshwari, Sachin S. Sapatnekar: Minimum area retiming with equivalent initial states. 216-219
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  Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev: Decomposition and technology mapping of speed-independent circuits using Boolean relations. 220-227
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  Chuck Monahan, Forrest Brewer: Scheduling and binding bounds for RT-level symbolic execution. 230-235
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  Chih-Tung Chen, Kayhan Küçükçakar: High-level scheduling model and control synthesis for a broad range of design applications. 236-243
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  Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha: Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. 244-250
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  Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal: Optimal wire and transistor sizing for circuits with non-tree topology. 252-259
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  Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani: Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. 260-265
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  Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. 266-273
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  J. Richard Griffith, Michel S. Nakhla: A new high-order absolutely-stable explicit numerical integration algorithm for the time-domain simulation of nonlinear circuits. 276-280
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  Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu: Circuit optimization via adjoint Lagrangians. 281-288
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  Tuyen V. Nguyen, Anirudh Devgan: State transformation in event driven explicit simulation. 289-294
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  Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A fast and robust exact algorithm for face embedding. 296-303
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  Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey: An output encoding problem and a solution technique. 304-307
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  Robert M. Fuhrer, Steven M. Nowick: OPTIMIST: state minimization for optimal 2-level logic implementation. 308-315
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  Oliver Bringmann, Wolfgang Rosenstiel: Resource sharing in hierarchical synthesis. 318-325
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  Salil Raje, Reinaldo A. Bergamaschi: Generalized resource sharing. 326-332
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  Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Exploiting off-chip memory access modes in high-level synthesis. 333-340
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  Morgan Enos, Scott Hauck, Majid Sarrafzadeh: Replication for logic bipartitioning. 342-349
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  Shantanu Dutt, Halim Theny: Partitioning around roadblocks: tackling constraints with intermediate relaxations. 350-355
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  Wray L. Buntine, Lixin Su, A. Richard Newton, Andrew Mayer: Adaptive methods for netlist partitioning. 356-363
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  C.-J. Richard Shi, Xiang-Dong Tan: Symbolic analysis of large analog circuits with determinant decision diagrams. 366-373
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  Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen: A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. 374-381
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  Pramodchandran N. Variyam, Abhijit Chatterjee: Test generation for comprehensive testing of linear analog circuits using transient response sampling. 382-385
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  Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Reachability analysis using partitioned-ROBDDs. 388-393
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  Dominik Stoffel, Wolfgang Kunz: Record & play: a structural fixed point iteration for sequential circuit verification. 394-399
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  Hiroaki Iwashita, Tsuneo Nakata: Forward model checking techniques oriented to buggy designs. 400-404
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  Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for faults in system backplanes. 406-413
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  Christos A. Papachristou, Mikhail Baklashov: A test synthesis technique using redundant register transfers. 414-420
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  Irith Pomeranz, Sudhakar M. Reddy: Built-in test generation for synchronous sequential circuits. 421-426
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  Vi Chi Chan, David Lewis: Hierarchical partitioning for field-programmable systems. 428-435
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  Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag: Hybrid spectral/iterative partitioning. 436-440
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  Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu: Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. 441-446
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  Sharad Kapur, David E. Long: IES3: a fast integral equation solver for efficient 3-dimensional extraction. 448-455
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  Mattan Kamon, Nuno Alexandre Marques, Jacob White: FastPep: a fast parasitic extraction program for complex three-dimensional geometries. 456-460
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  Ranjit Gharpurey, Srinath Hosur: Transform domain techniques for efficient extraction of substrate parasitics. 461-467
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  Mark D. Spiller, A. Richard Newton: EDA and the network. 470-476
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  Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. 478-485
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  Joseph N. Kozhaya, Farid N. Najm: Accurate power estimation for large sequential circuits. 488-493
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  Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi: Fast power estimation for deterministic input streams. 494-501
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  Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou: A power modeling and characterization method for macrocells using structure information. 502-506
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  Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya: Transformational partitioning for co-design of multiprocessor systems. 508-515
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  Asawaree Kalavade, P. A. Subrahmanyam: Hardware/software partitioning for multi-function systems. 516-521
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  Robert P. Dick, Niraj K. Jha: MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. 522-529
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  Majid Sarrafzadeh, Maogang Wang: NRG: global and detailed placement. 532-537
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  Shinji Sato: Simulated quenching: a new placement method for module generation. 538-541
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  Srinivasa Rao Arikati, Ravi Varadarajan: A signature based approach to regularity extraction. 542-545
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  Haluk Konuk: Fault simulation of interconnect opens in digital CMOS circuits. 548-554
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  Tzuhao Chen, Ibrahim N. Hajj: GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. 555-561
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  Srikanth Venkataraman, W. Kent Fuchs: A deductive technique for diagnosis of bridging faults. 562-567
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  Unni Narayanan, C. L. Liu: Low power logic synthesis for XOR based circuits. 570-574
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  Hai Zhou, D. F. Wong: An exact gate decomposition algorithm for low-power technology mapping. 575-580
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  Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli: Trace driven logic synthesis&mdashapplication to power minimization. 581-588
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  Sujit Dey, Surendra Bommu: Performance analysis of a system of communicating processes. 590-597
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  Rolf Ernst, Wei Ye: Embedded program timing analysis based on path clustering and architecture classification. 598-604
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  Vincent John Mooney III, Giovanni De Micheli: Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system. 605-612
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  Chris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. 614-621
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  Youxin Gao, D. F. Wong: Optimal shape function for a bi-directional wire under Elmore delay model. 622-627
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  Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. 628-633
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  Ramesh C. Tekumalla, Premachandran R. Menon: Test generation for primitive path delay faults in combinational circuits. 636-641
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  Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Fast identification of untestable delay faults using implications. 642-647
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  Paul Tafertshofer, Andreas Ganz, Manfred Henftling: A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. 648-655
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  Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. 658-662
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  Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Logic synthesis for large pass transistor circuits. 663-670
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  Jinan Lou, Amir H. Salek, Massoud Pedram: An exact solution to simultaneous technology mapping and linear placement problem. 671-675
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  Sang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo: An efficient statistical analysis methodology and its application to high-density DRAMs. 678-683
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  Vladimir Székely, Márta Rencz: Fast field solver-programs for thermal and electrostatic analysis of microsystem elements. 684-689
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  Rachid Helaihel, Kunle Olukotun: Java as a specification language for hardware-software systems. 690-697
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  Jeffrey Z. Su, Wayne Wei-Ming Dai: Post-route optimization for improved yield using a rubber-band wiring model. 700-706
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  Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin: Delay bounded buffered tree construction for timing driven floorplanning. 707-712
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  Jason Cong, Cheng-Kok Koh: Interconnect layout optimization under higher-order RLC model. 713-720
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  Sying-Jyan Wang, Tsi-Ming Tsai: Test and diagnosis of fault logic blocks in FPGAs. 722-727
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  Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin: Partial scan delay fault testing of asynchronous circuits. 728-735
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  Dimitrios Kagaris, Spyros Tragoudas: Maximum independent sets on transitive graphs and their applications in testing and CAD. 736-740
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  Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün: Verifying hardware in its software context. 742-749
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  Kenneth S. Kundert: Simulation methods for RF integrated circuits. 752-765
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  Anirudh Devgan, Leon Stok, Sandip Kundu: Timing analysis and optimization: from devices to systems (tutorial).
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  Rajesh K. Gupta, Mani B. Srivastava: Design technology for building wireless systems (tutorial).
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  Raul Camposano, Andrew Seawright, Joseph Buck: Modeling and synthesis of behavior, control and dataflow (tutorial).
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  Wayne Wei-Ming Dai, Howard L. Kalter, Rob Roy, Wayne Wolf: Critical technologies and methodologies for systems-on-chips (tutorial).