ICCAD 1998:
San Jose, California, USA
International Conference on Computer-Aided Design, November 8-12, 1998, San Jose, CA, USA. ACM and IEEE Computer Society, 1998
- Soren Hein, Vijay Nagasamy, Bernhard Rohfleisch, Christoforos E. Kozyrakis, Nikil D. Dutt, Francky Catthoor:
Embedded memories in system design - from technology to systems architecture.
1

- Serge Hustin, Miodrag Potkonjak, Eric Verhulst, Wayne Wolf:
Real-time operating systems for embedded computing.
2

- Sujit Dey, Jacob A. Abraham, Yervant Zorian:
High-level design validation and test.
3

- Phillip Restle, Joel R. Phillips, Ibrahim M. Elfadel:
Interconnect in high speed designs: problems, methodologies and tools.
4

- Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf:
How will CAD handle billion-transistor systems? (panel).
5

- Tong Li, Ching-Han Tsai, Sung-Mo Kang:
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress.
6-11

- Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh:
Simulation of coupling capacitances using matrix partitioning.
12-18

- Tao Lin, Emrah Acar, Lawrence T. Pileggi:
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response.
19-25

- Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Wireplanning in logic synthesis.
26-33

- Yao-Wen Chang, Jai-Ming Lin, D. F. Wong:
Graph matching-based algorithms for FPGA segmentation design.
34-39

- Jason Cong, Songjie Xu:
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources.
40-44

- Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Borriello:
Control generation for embedded systems based on composition of modal processes.
46-53

- Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele:
Representation of process mode correlation for scheduling.
54-61

- Robert P. Dick, Niraj K. Jha:
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems.
62-67

- Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Synthesis of BIST hardware for performance testing of MCM interconnections.
69-73

- Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang:
Using a single input to support multiple scan chains.
74-78

- Frank F. Hsu, Janak H. Patel:
High-level variable selection for partial-scan implementation.
79-84

- Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh:
Multipoint moment matching model for multiport distributed interconnect networks.
85-91

- Jaijeet S. Roychowdhury:
Reduced-order modelling of linear time-varying systems.
92-95

- Joel R. Phillips:
Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors.
96-102

- Subarnarekha Sinha, Robert K. Brayton:
Implementation and use of SPFDs in optimizing Boolean networks.
103-110

- Shin-ichi Minato, Giovanni De Micheli:
Finding all simple disjunctive decompositions using irredundant sum-of-products forms.
111-117

- Yusuke Matsunaga:
On accelerating pattern matching for technology mapping.
118-122

- Prashant Saxena, C. L. Liu:
A performance-driven layer assignment algorithm for multiple interconnect trees.
124-127

- Avaneendra Gupta, John P. Hayes:
Optimal 2-D cell layout with integrated transistor folding.
128-135

- Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin:
Integrating logic retiming and register placement.
136-139

- Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy:
Static compaction using overlapped restoration and segment pruning.
140-146

- Vamsi Boppana, W. Kent Fuchs:
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits.
147-154

- Michael S. Hsiao:
A fast, accurate, and non-statistical method for fault coverage estimation.
155-161

- Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov:
Simulation of high-Q oscillators.
162-169

- Alper Demir:
Phase noise in oscillators: DAEs and colored noise sources.
170-177

- Sharad Kapur, David E. Long:
High-order Nyström schemes for efficient 3-D capacitance extraction.
178-185

- John Lach, William H. Mangione-Smith, Miodrag Potkonjak:
Signature hiding techniques for FPGA intellectual property protection.
186-189

- Gang Qu, Miodrag Potkonjak:
Analysis of watermarking techniques for graph coloring problem.
190-193

- Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong:
Intellectual property protection by watermarking combinational logic synthesis solutions.
194-198

- Jaijeet S. Roychowdhury, Alper Demir:
Estimating noise in RF systems.
199-202

- Dennis Sylvester, Kurt Keutzer:
Getting to the bottom of deep submicron.
203-211

- Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi:
Determination of worst-case aggressor alignment for delay calculation.
212-219

- Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah:
Noise considerations in circuit optimization.
220-227

- Rajamohana Hegde, Naresh R. Shanbhag:
Energy-efficiency in presence of deep submicron noise.
228-234

- Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi:
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.
235-241

- Tyler Thorp, Gin Yee, Carl Sechen:
Domino logic synthesis using complex static gates.
242-247

- Min Zhao, Sachin S. Sapatnekar:
Technology mapping for domino logic.
248-251

- Fung Yu Young, D. F. Wong:
Slicing floorplans with pre-placed modules.
252-258

- Maggie Zhiwei Kang, Wayne Wei-Ming Dai:
Arbitrary rectilinear block packing based on sequence pair.
259-266

- Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani:
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.
267-274

- Ramesh C. Tekumalla, Premachandran R. Menon:
On primitive fault test generation in non-scan sequential circuits.
275-282

- Ilker Hamzaoglu, Janak H. Patel:
Test set compaction algorithms for combinational circuits.
283-289

- Chauchin Su:
A linear optimal test generation algorithm for interconnect testing.
290-295

- Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee:
GPCAD: a tool for CMOS op-amp synthesis.
296-303

- Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen:
An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits.
304-307

- Geert Debyser, Georges G. E. Gielen:
Efficient analog circuit synthesis with simultaneous yield and robustness optimization.
308-311

- Balakrishnan Iyer, Maciej J. Ciesielski:
Reencoding for cycle-time minimization under fixed encoding length.
312-315

- Soha Hassoun, Carl Ebeling:
Using precomputation in architecture and logic resynthesis.
316-323

- Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev:
Lazy transition systems: application to timing optimization of asynchronous circuits.
324-331

- Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta:
A general approach for regularity extraction in datapath circuits.
332-339

- Luc Séméria, Giovanni De Micheli:
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C.
340-346

- Chunho Lee, Miodrag Potkonjak:
A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis.
347-351

- In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley:
Approximate reachability don't cares for CTL model checking.
351-358

- Gila Kamhi, Limor Fix:
Adaptive variable reordering for symbolic model checking.
359-365

- Shankar G. Govindaraju, David L. Dill:
Verification by approximate forward and backward reachability.
366-370

- Ravindranath Naiknaware, Terri S. Fiez:
CMOS analog circuit stack generation with matching constraints.
371-375

- Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang:
Testability analysis and multi-frequency ATPG for analog circuits and systems.
376-383

- Junwei Hou, Abhijit Chatterjee:
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits.
384-391

- Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe:
Waiting false path analysis of sequential logic circuits for performance optimization.
392-395

- Marios C. Papaefthymiou:
Asymptotically efficient retiming under setup and hold constraints.
396-401

- Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
On the optimization power of retiming and resynthesis transformations.
402-407

- Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Architecture driven circuit partitioning.
408-411

- Shantanu Tarafdar, Miriam Leeser, Zixin Yin:
Integrating floorplanning in data-transfer based high-level synthesis.
412-417

- Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita:
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.
418-425

- Yih-Chih Chou, Youn-Long Lin:
A graph-partitioning-based approach for multi-layer constrained via minimization.
426-429

- Yanbing Li, Wayne Wolf:
Hardware/software co-synthesis with memory hierarchies.
430-436

- Ross B. Ortega, Gaetano Borriello:
Communication synthesis for distributed embedded systems.
437-444

- Kayhan Küçükçakar:
Analysis of emerging core-based design lifecycle.
445-449

- Enno Wein:
Core integration: overview and challenges.
450-452

- Resve A. Saleh, David Overhauser, Sandy Taylor:
Full-chip verification of UDSM designs.
453-460

- Alessandro Bogliolo, Luca Benini:
Node sampling: a robust RTL power modeling approach.
461-467

- Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power sensitivity in sequential circuits with power macromodeling application.
468-472

- Ali Pinar, C. L. Liu:
Power invariant vector sequence compaction.
473-476

- Steve Haynal, Forrest Brewer:
Efficient encoding for exact symbolic automata-based scheduling.
477-481

- Jorge M. Pena, Arlindo L. Oliveira:
A new algorithm for the reduction of incompletely specified finite state machines.
482-489

- Qi Wang, Sarma B. K. Vrudhula:
Static power optimization of deep submicron CMOS circuits for dual VT technology.
490-496

- Huiqun Liu, D. F. Wong:
Network flow based circuit partitioning for time-multiplexed FPGAs.
497-504

- Sverre Wichlund:
On multilevel circuit partitioning.
505-511

- Jason Cong, Sung Kyu Lim:
Multiway partitioning with pairwise movement.
512-516

- Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow.
517-524

- Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra:
Functional debugging of systems-on-chip.
525-528

- Pei-Hsin Ho, Adrian J. Isles, Timothy Kam:
Formal verification of pipeline control using controlled token nets and abstract interpretation.
529-536

- Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru:
Proposal of a timing model for CMOS logic gates driving a CRC load.
537-544

- Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok:
Gate-size selection for standard cell libraries.
545-550

- Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni:
Fanout optimization under a submicron transistor-level delay model.
551-556

- Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using retiming.
557-562

- Jerry R. Burch, Vigyan Singhal:
Robust latch mapping for combinational equivalence checking.
563-569

- Jerry R. Burch, Vigyan Singhal:
Tight integration of combinational verification methods.
570-576

- Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.
577-584

- Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp:
Period assignment in multidimensional periodic scheduling.
585-592

- M. Narasimhan, J. Ramanujam:
Improving the computational performance of ILP-based problems.
593-596

- Gang Qu, Miodrag Potkonjak:
Techniques for energy minimization of communication pipelines.
597-600

- Sumit Roy, Harm Arts, Prithviraj Banerjee:
PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis.
601-606

- Efstathios D. Kyriakis-Bitzaros, Spiridon Nikolaidis, Anna Tatsaki:
Accurate calculation of bit-level transition activity using word-level statistics and entropy function.
607-610

- Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize delay using transmission line model.
611-616

- Chung-Ping Chen, Chris C. N. Chu, D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
617-624

- Amir H. Salek, Jinan Lou, Massoud Pedram:
A simultaneous routing tree construction and fanout optimization algorithm.
625-630

- Jawahar Jain, William Adams, Masahiro Fujita:
Sampling schemes for computing OBDD variable orderings.
631-638

- David E. Long:
The design of a cache-friendly BDD library.
639-645

- Justin E. Harlow III, Franc Brglez:
Design of experiments in BDD variable ordering: lessons learned.
646-652

- Inki Hong, Miodrag Potkonjak, Mani B. Srivastava:
On-line scheduling of hard real-time tasks on variable voltage processor.
653-656

- Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Transforming control-flow intensive designs to facilitate power management.
657-664

- Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park:
Synthesis of application specific instructions for embedded DSP software.
665-671

- Christoph Scholl, Bernd Becker, Thomas M. Weis:
Word-level decision diagrams, WLCDs and division.
672-677

- James Smith, Giovanni De Micheli:
Polynomial methods for component matching and verification.
678-685

- Karsten Strehl, Lothar Thiele:
Symbolic model checking of process networks using interval diagram techniques.
686-692

- Gaetano Borriello, Luciano Lavagno, Ross B. Ortega:
Interface synthesis: a vertical slice from digital logic to software components.
693-695

- Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
Dynamic power management of electronic systems.
696-702

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